Patchwork [U-Boot] powerpc mpc85xx: Do not protect TLB entry for debuggging in AS1 against invalidation

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Submitter Laurent Joye
Date Sept. 7, 2012, 12:50 p.m.
Message ID <6670B5959A1255459E98630A607295B473CC2B@hrsrv31.haslerrail.net>
Download mbox | patch
Permalink /patch/182375/
State Changes Requested
Delegated to: Andy Fleming
Headers show

Comments

Laurent Joye - Sept. 7, 2012, 12:50 p.m.
In case of booting from RAM (CONFIG_SYS_RAMBOOT), a TLB entry is created
for IVPR + IVOR15 to map on valid OP code address.
This TLB entry shall not be protected against invalidation, because
a new TLB entry to access RAM in AS0 will be created by
cpu_init_early_f.
If this TLB entry is protected against invalidation, this will creates
2 TLB for the same address range (forbidden).

Signed-off-by: Laurent Joye <laurent.joye@haslerrail.com>
---
 arch/powerpc/cpu/mpc85xx/start.S |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

        ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,
Scott Wood - Sept. 7, 2012, 7:50 p.m.
On 09/07/2012 07:50 AM, Joye Laurent wrote:
> In case of booting from RAM (CONFIG_SYS_RAMBOOT), a TLB entry is created
> for IVPR + IVOR15 to map on valid OP code address.
> This TLB entry shall not be protected against invalidation, because
> a new TLB entry to access RAM in AS0 will be created by
> cpu_init_early_f.
> If this TLB entry is protected against invalidation, this will creates
> 2 TLB for the same address range (forbidden).

Instead we should explicitly remove the debug TLB when it is no longer
needed.

-Scott

Patch

diff --git a/arch/powerpc/cpu/mpc85xx/start.S
b/arch/powerpc/cpu/mpc85xx/start.S
index 6aabc30..56c4ee7 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -229,8 +229,8 @@  l2_disabled:
  * TLB entry is created for IVPR + IVOR15 to map on valid OP code
address
  * because "nexti" will resize TLB to 4K
  */
-       lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@h
-       ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@l
+       lis     r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_256K)@h
+       ori     r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_256K)@l
 
        lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I))@h