| Message ID | 1346877673-9136-5-git-send-email-ehabkost@redhat.com |
|---|---|
| State | New |
| Headers | show |
On Wed, 5 Sep 2012 17:41:10 -0300 Eduardo Habkost <ehabkost@redhat.com> wrote: > Those models are maintained by QEMU and may require compatibility code > to be added when making some changes. Keeping the data in the C source > code should make it simpler to handle those details. > > Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> > --- > sysconfigs/target/cpus-x86_64.conf | 129 +--------------------- > target-i386/cpu.c | 219 > +++++++++++++++++++++++++++++++++++++ 2 files changed, 220 insertions(+), > 128 deletions(-) > > diff --git a/sysconfigs/target/cpus-x86_64.conf > b/sysconfigs/target/cpus-x86_64.conf index cee0ea9..3902189 100644 > --- a/sysconfigs/target/cpus-x86_64.conf > +++ b/sysconfigs/target/cpus-x86_64.conf > @@ -1,128 +1 @@ > -# x86 CPU MODELS > - > -[cpudef] > - name = "Conroe" > - level = "2" > - vendor = "GenuineIntel" > - family = "6" > - model = "2" > - stepping = "3" > - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr > sep apic cx8 mce pae msr tsc pse de fpu" > - feature_ecx = "ssse3 sse3" > - extfeature_edx = "i64 xd syscall" ... > + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | > CPUID_EXT2_SYSCALL, Silent fix, replacing i64 with CPUID_EXT2_LM looks like "i64" is mistake and never worked. In Intel & AMD cpuid guides 01.EDX[30] is reserved and what was probably meant/intended here is to use 80000001h.EDX[29] /* CPUID_EXT2_LM */ Perhaps patch that fixes it ought to go before this one.
On Mon, 10 Sep 2012 14:18:38 +0200 Igor Mammedov <imammedo@redhat.com> wrote: > On Wed, 5 Sep 2012 17:41:10 -0300 > Eduardo Habkost <ehabkost@redhat.com> wrote: > > > Those models are maintained by QEMU and may require compatibility code > > to be added when making some changes. Keeping the data in the C source > > code should make it simpler to handle those details. > > > > Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> > > --- > > sysconfigs/target/cpus-x86_64.conf | 129 +--------------------- > > target-i386/cpu.c | 219 > > +++++++++++++++++++++++++++++++++++++ 2 files changed, 220 insertions(+), > > 128 deletions(-) > > > > diff --git a/sysconfigs/target/cpus-x86_64.conf > > b/sysconfigs/target/cpus-x86_64.conf index cee0ea9..3902189 100644 > > --- a/sysconfigs/target/cpus-x86_64.conf > > +++ b/sysconfigs/target/cpus-x86_64.conf > > @@ -1,128 +1 @@ > > -# x86 CPU MODELS > > - > > -[cpudef] > > - name = "Conroe" > > - level = "2" > > - vendor = "GenuineIntel" > > - family = "6" > > - model = "2" > > - stepping = "3" > > - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr > > sep apic cx8 mce pae msr tsc pse de fpu" > > - feature_ecx = "ssse3 sse3" > > - extfeature_edx = "i64 xd syscall" > ... > > + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | > > CPUID_EXT2_SYSCALL, > Silent fix, replacing i64 with CPUID_EXT2_LM > looks like "i64" is mistake and never worked. In Intel & AMD cpuid guides Actually it works when setting feature fields because it uses setfeatures(), however setting i64 will set wrong bit if it's set using add_flagname_to_bitmaps() > 01.EDX[30] is reserved and what was probably meant/intended here is to use > 80000001h.EDX[29] /* CPUID_EXT2_LM */ > Perhaps patch that fixes it ought to go before this one. >
On Mon, 10 Sep 2012 14:31:49 +0200 Igor Mammedov <imammedo@redhat.com> wrote: > On Mon, 10 Sep 2012 14:18:38 +0200 > Igor Mammedov <imammedo@redhat.com> wrote: > > > On Wed, 5 Sep 2012 17:41:10 -0300 > > Eduardo Habkost <ehabkost@redhat.com> wrote: > > > > > Those models are maintained by QEMU and may require compatibility code > > > to be added when making some changes. Keeping the data in the C source > > > code should make it simpler to handle those details. > > > > > > Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> > > > --- > > > sysconfigs/target/cpus-x86_64.conf | 129 +--------------------- > > > target-i386/cpu.c | 219 > > > +++++++++++++++++++++++++++++++++++++ 2 files changed, 220 > > > insertions(+), 128 deletions(-) > > > > > > diff --git a/sysconfigs/target/cpus-x86_64.conf > > > b/sysconfigs/target/cpus-x86_64.conf index cee0ea9..3902189 100644 > > > --- a/sysconfigs/target/cpus-x86_64.conf > > > +++ b/sysconfigs/target/cpus-x86_64.conf > > > @@ -1,128 +1 @@ > > > -# x86 CPU MODELS > > > - > > > -[cpudef] > > > - name = "Conroe" > > > - level = "2" > > > - vendor = "GenuineIntel" > > > - family = "6" > > > - model = "2" > > > - stepping = "3" > > > - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr > > > sep apic cx8 mce pae msr tsc pse de fpu" > > > - feature_ecx = "ssse3 sse3" > > > - extfeature_edx = "i64 xd syscall" > > ... > > > + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | > > > CPUID_EXT2_SYSCALL, > > Silent fix, replacing i64 with CPUID_EXT2_LM > > looks like "i64" is mistake and never worked. In Intel & AMD cpuid guides > Actually it works when setting feature fields because it uses > setfeatures(), however setting i64 will set wrong bit if it's set using > add_flagname_to_bitmaps() I'm wrong, and sorry for noise. I mixed up ia64 from feature_name with i64 from ext2_feature_name. But question unrelated to this patch is still stand if ia64 is valid bit for 01.EDX[30]?
On Wed, 5 Sep 2012 17:41:10 -0300 Eduardo Habkost <ehabkost@redhat.com> wrote: > Those models are maintained by QEMU and may require compatibility code > to be added when making some changes. Keeping the data in the C source > code should make it simpler to handle those details. > > Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> > --- > sysconfigs/target/cpus-x86_64.conf | 129 +--------------------- > target-i386/cpu.c | 219 > +++++++++++++++++++++++++++++++++++++ 2 files changed, 220 insertions(+), > 128 deletions(-) > > diff --git a/sysconfigs/target/cpus-x86_64.conf > b/sysconfigs/target/cpus-x86_64.conf index cee0ea9..3902189 100644 > --- a/sysconfigs/target/cpus-x86_64.conf > +++ b/sysconfigs/target/cpus-x86_64.conf > @@ -1,128 +1 @@ > -# x86 CPU MODELS > - > -[cpudef] > - name = "Conroe" > - level = "2" > - vendor = "GenuineIntel" > - family = "6" > - model = "2" > - stepping = "3" > - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr > sep apic cx8 mce pae msr tsc pse de fpu" > - feature_ecx = "ssse3 sse3" > - extfeature_edx = "i64 xd syscall" > - extfeature_ecx = "lahf_lm" > - xlevel = "0x8000000A" > - model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)" > - > -[cpudef] > - name = "Penryn" > - level = "2" > - vendor = "GenuineIntel" > - family = "6" > - model = "2" > - stepping = "3" > - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr > sep apic cx8 mce pae msr tsc pse de fpu" > - feature_ecx = "sse4.1 cx16 ssse3 sse3" > - extfeature_edx = "i64 xd syscall" > - extfeature_ecx = "lahf_lm" > - xlevel = "0x8000000A" > - model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)" > - > -[cpudef] > - name = "Nehalem" > - level = "2" > - vendor = "GenuineIntel" > - family = "6" > - model = "2" > - stepping = "3" > - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr > sep apic cx8 mce pae msr tsc pse de fpu" > - feature_ecx = "popcnt sse4.2 sse4.1 cx16 ssse3 sse3" > - extfeature_edx = "i64 syscall xd" > - extfeature_ecx = "lahf_lm" > - xlevel = "0x8000000A" > - model_id = "Intel Core i7 9xx (Nehalem Class Core i7)" > - > -[cpudef] > - name = "Westmere" > - level = "11" > - vendor = "GenuineIntel" > - family = "6" > - model = "44" > - stepping = "1" > - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr > sep apic cx8 mce pae msr tsc pse de fpu" > - feature_ecx = "aes popcnt sse4.2 sse4.1 cx16 ssse3 sse3" > - extfeature_edx = "i64 syscall xd" > - extfeature_ecx = "lahf_lm" > - xlevel = "0x8000000A" > - model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)" > - > -[cpudef] > - name = "SandyBridge" > - level = "0xd" > - vendor = "GenuineIntel" > - family = "6" > - model = "42" > - stepping = "1" > - feature_edx = " sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr > sep apic cx8 mce pae msr tsc pse de fpu" > - feature_ecx = "avx xsave aes tsc-deadline popcnt x2apic sse4.2 sse4.1 > cx16 ssse3 pclmulqdq sse3" > - extfeature_edx = "i64 rdtscp nx syscall " > - extfeature_ecx = "lahf_lm" > - xlevel = "0x8000000A" > - model_id = "Intel Xeon E312xx (Sandy Bridge)" > - > -[cpudef] > - name = "Opteron_G1" > - level = "5" > - vendor = "AuthenticAMD" > - family = "15" > - model = "6" > - stepping = "1" > - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr > sep apic cx8 mce pae msr tsc pse de fpu" > - feature_ecx = "sse3" > - extfeature_edx = "lm fxsr mmx nx pse36 pat cmov mca pge mtrr syscall > apic cx8 mce pae msr tsc pse de fpu" > - extfeature_ecx = " " > - xlevel = "0x80000008" > - model_id = "AMD Opteron 240 (Gen 1 Class Opteron)" > - > -[cpudef] > - name = "Opteron_G2" > - level = "5" > - vendor = "AuthenticAMD" > - family = "15" > - model = "6" > - stepping = "1" > - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr > sep apic cx8 mce pae msr tsc pse de fpu" > - feature_ecx = "cx16 sse3" > - extfeature_edx = "lm rdtscp fxsr mmx nx pse36 pat cmov mca pge mtrr > syscall apic cx8 mce pae msr tsc pse de fpu" > - extfeature_ecx = "svm lahf_lm" > - xlevel = "0x80000008" > - model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)" > - > -[cpudef] > - name = "Opteron_G3" > - level = "5" > - vendor = "AuthenticAMD" > - family = "15" > - model = "6" > - stepping = "1" > - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr > sep apic cx8 mce pae msr tsc pse de fpu" > - feature_ecx = "popcnt cx16 monitor sse3" > - extfeature_edx = "lm rdtscp fxsr mmx nx pse36 pat cmov mca pge mtrr > syscall apic cx8 mce pae msr tsc pse de fpu" > - extfeature_ecx = "misalignsse sse4a abm svm lahf_lm" > - xlevel = "0x80000008" > - model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)" > - > -[cpudef] > - name = "Opteron_G4" > - level = "0xd" > - vendor = "AuthenticAMD" > - family = "21" > - model = "1" > - stepping = "2" > - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr > sep apic cx8 mce pae msr tsc pse de fpu" > - feature_ecx = "avx xsave aes popcnt sse4.2 sse4.1 cx16 ssse3 pclmulqdq > sse3" > - extfeature_edx = "lm rdtscp pdpe1gb fxsr mmx nx pse36 pat cmov mca pge > mtrr syscall apic cx8 mce pae msr tsc pse de fpu" > - extfeature_ecx = " fma4 xop 3dnowprefetch misalignsse sse4a abm svm > lahf_lm" > - xlevel = "0x8000001A" > - model_id = "AMD Opteron 62xx class CPU" > - > +# The CPU models from this file are now built-in in the QEMU source code > diff --git a/target-i386/cpu.c b/target-i386/cpu.c > index d2af0ff..73302d8 100644 > --- a/target-i386/cpu.c > +++ b/target-i386/cpu.c > @@ -490,6 +490,225 @@ static x86_def_t builtin_x86_defs[] = { > .xlevel = 0x8000000A, > .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", > }, > + { > + .name = "Conroe", > + .level = 2, > + .vendor1 = CPUID_VENDOR_INTEL_1, > + .vendor2 = CPUID_VENDOR_INTEL_2, > + .vendor3 = CPUID_VENDOR_INTEL_3, > + .family = 6, > + .model = 2, > + .stepping = 3, > + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | > + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | > CPUID_MCA | > + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | > + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | > + CPUID_DE | CPUID_FP87, > + .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, > + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | > CPUID_EXT2_SYSCALL, > + .ext3_features = CPUID_EXT3_LAHF_LM, > + .xlevel = 0x8000000A, > + .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", > + }, > + { > + .name = "Penryn", > + .level = 2, > + .vendor1 = CPUID_VENDOR_INTEL_1, > + .vendor2 = CPUID_VENDOR_INTEL_2, > + .vendor3 = CPUID_VENDOR_INTEL_3, > + .family = 6, > + .model = 2, > + .stepping = 3, > + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | > + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | > CPUID_MCA | > + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | > + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | > + CPUID_DE | CPUID_FP87, > + .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 > | > + CPUID_EXT_SSE3, > + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | > CPUID_EXT2_SYSCALL, > + .ext3_features = CPUID_EXT3_LAHF_LM, > + .xlevel = 0x8000000A, > + .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", > + }, > + { > + .name = "Nehalem", > + .level = 2, > + .vendor1 = CPUID_VENDOR_INTEL_1, > + .vendor2 = CPUID_VENDOR_INTEL_2, > + .vendor3 = CPUID_VENDOR_INTEL_3, > + .family = 6, > + .model = 2, > + .stepping = 3, > + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | > + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | > CPUID_MCA | > + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | > + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | > + CPUID_DE | CPUID_FP87, > + .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | > CPUID_EXT_SSE41 | > + CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, > + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | > CPUID_EXT2_NX, > + .ext3_features = CPUID_EXT3_LAHF_LM, > + .xlevel = 0x8000000A, > + .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", > + }, > + { > + .name = "Westmere", > + .level = 11, > + .vendor1 = CPUID_VENDOR_INTEL_1, > + .vendor2 = CPUID_VENDOR_INTEL_2, > + .vendor3 = CPUID_VENDOR_INTEL_3, > + .family = 6, > + .model = 44, > + .stepping = 1, > + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | > + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | > CPUID_MCA | > + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | > + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | > + CPUID_DE | CPUID_FP87, > + .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 > | > + CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | > + CPUID_EXT_SSE3, > + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | > CPUID_EXT2_NX, > + .ext3_features = CPUID_EXT3_LAHF_LM, > + .xlevel = 0x8000000A, > + .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", > + }, > + { > + .name = "SandyBridge", > + .level = 0xd, > + .vendor1 = CPUID_VENDOR_INTEL_1, > + .vendor2 = CPUID_VENDOR_INTEL_2, > + .vendor3 = CPUID_VENDOR_INTEL_3, > + .family = 6, > + .model = 42, > + .stepping = 1, > + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | > + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | > CPUID_MCA | > + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | > + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | > + CPUID_DE | CPUID_FP87, > + .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | > + CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | > + CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | > + CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | > + CPUID_EXT_SSE3, > + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX > | > + CPUID_EXT2_SYSCALL, > + .ext3_features = CPUID_EXT3_LAHF_LM, > + .xlevel = 0x8000000A, > + .model_id = "Intel Xeon E312xx (Sandy Bridge)", > + }, > + { > + .name = "Opteron_G1", > + .level = 5, > + .vendor1 = CPUID_VENDOR_AMD_1, > + .vendor2 = CPUID_VENDOR_AMD_2, > + .vendor3 = CPUID_VENDOR_AMD_3, > + .family = 15, > + .model = 6, > + .stepping = 1, > + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | > + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | > CPUID_MCA | > + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | > + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | > + CPUID_DE | CPUID_FP87, > + .ext_features = CPUID_EXT_SSE3, > + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX | > + CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT | > + CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE | > + CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC | > + CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | > CPUID_EXT2_MSR | > + CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | > CPUID_EXT2_FPU, > + .xlevel = 0x80000008, > + .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", > + }, > + { > + .name = "Opteron_G2", > + .level = 5, > + .vendor1 = CPUID_VENDOR_AMD_1, > + .vendor2 = CPUID_VENDOR_AMD_2, > + .vendor3 = CPUID_VENDOR_AMD_3, > + .family = 15, > + .model = 6, > + .stepping = 1, > + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | > + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | > CPUID_MCA | > + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | > + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | > + CPUID_DE | CPUID_FP87, > + .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3, > + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | > CPUID_EXT2_FXSR | > + CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 | > + CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA | > + CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | > + CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE | > + CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | > CPUID_EXT2_PSE | > + CPUID_EXT2_DE | CPUID_EXT2_FPU, > + .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, > + .xlevel = 0x80000008, > + .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", > + }, > + { > + .name = "Opteron_G3", > + .level = 5, > + .vendor1 = CPUID_VENDOR_AMD_1, > + .vendor2 = CPUID_VENDOR_AMD_2, > + .vendor3 = CPUID_VENDOR_AMD_3, > + .family = 15, > + .model = 6, > + .stepping = 1, > + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | > + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | > CPUID_MCA | > + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | > + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | > + CPUID_DE | CPUID_FP87, > + .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 | > CPUID_EXT_MONITOR | > + CPUID_EXT_SSE3, > + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | > CPUID_EXT2_FXSR | > + CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 | > + CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA | > + CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | > + CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE | > + CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | > CPUID_EXT2_PSE | > + CPUID_EXT2_DE | CPUID_EXT2_FPU, > + .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | > + CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, > + .xlevel = 0x80000008, > + .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", > + }, > + { > + .name = "Opteron_G4", > + .level = 0xd, > + .vendor1 = CPUID_VENDOR_AMD_1, > + .vendor2 = CPUID_VENDOR_AMD_2, > + .vendor3 = CPUID_VENDOR_AMD_3, > + .family = 21, > + .model = 1, > + .stepping = 2, > + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | > + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | > CPUID_MCA | > + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | > + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | > + CPUID_DE | CPUID_FP87, > + .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | > + CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | > + CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | > + CPUID_EXT_SSE3, > + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | > + CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX | > + CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT | > + CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE | > + CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC | > + CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | > CPUID_EXT2_MSR | > + CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | > CPUID_EXT2_FPU, > + .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | > + CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | > + CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | > + CPUID_EXT3_LAHF_LM, > + .xlevel = 0x8000001A, > + .model_id = "AMD Opteron 62xx class CPU", > + }, > }; > > static int cpu_x86_fill_model_id(char *str) Reviewed-by: Igor Mammedov <imammedo@redhat.com>
On 09/10/12 09:04, Igor Mammedov wrote: > On Mon, 10 Sep 2012 14:31:49 +0200 > Igor Mammedov <imammedo@redhat.com> wrote: > >> On Mon, 10 Sep 2012 14:18:38 +0200 >> Igor Mammedov <imammedo@redhat.com> wrote: >> >>> On Wed, 5 Sep 2012 17:41:10 -0300 >>> Eduardo Habkost <ehabkost@redhat.com> wrote: >>> >>>> Those models are maintained by QEMU and may require compatibility code >>>> to be added when making some changes. Keeping the data in the C source >>>> code should make it simpler to handle those details. >>>> >>>> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> >>>> --- >>>> sysconfigs/target/cpus-x86_64.conf | 129 +--------------------- >>>> target-i386/cpu.c | 219 >>>> +++++++++++++++++++++++++++++++++++++ 2 files changed, 220 >>>> insertions(+), 128 deletions(-) >>>> >>>> diff --git a/sysconfigs/target/cpus-x86_64.conf >>>> b/sysconfigs/target/cpus-x86_64.conf index cee0ea9..3902189 100644 >>>> --- a/sysconfigs/target/cpus-x86_64.conf >>>> +++ b/sysconfigs/target/cpus-x86_64.conf >>>> @@ -1,128 +1 @@ >>>> -# x86 CPU MODELS >>>> - >>>> -[cpudef] >>>> - name = "Conroe" >>>> - level = "2" >>>> - vendor = "GenuineIntel" >>>> - family = "6" >>>> - model = "2" >>>> - stepping = "3" >>>> - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr >>>> sep apic cx8 mce pae msr tsc pse de fpu" >>>> - feature_ecx = "ssse3 sse3" >>>> - extfeature_edx = "i64 xd syscall" >>> ... >>>> + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | >>>> CPUID_EXT2_SYSCALL, >>> Silent fix, replacing i64 with CPUID_EXT2_LM >>> looks like "i64" is mistake and never worked. In Intel & AMD cpuid guides >> Actually it works when setting feature fields because it uses >> setfeatures(), however setting i64 will set wrong bit if it's set using >> add_flagname_to_bitmaps() > I'm wrong, and sorry for noise. I mixed up ia64 from feature_name with i64 > from ext2_feature_name. > > But question unrelated to this patch is still stand if ia64 is valid bit for > 01.EDX[30]? > > Intel® Processor Identification and the CPUID Instruction Application Note 485 January 2006 Order Number: 241618-030 ... Updated Table 3-5 to include the feature flag definition (EDX[30]) for IA64 capabilities. ... 30 IA64 IA64 Capabilities The processor is a member of the Intel® Itanium® processor family and currently operating in IA32 emulation mode. --------------- Says that it is. Along with http://en.wikipedia.org/wiki/CPUID and http://www.sandpile.org/x86/cpuid.htm#level_0000_0001h (IA-64) But the newest version I found (241618-037, January 2011) is back to Reserved. -Don Slutz
Am 10.09.2012 16:50, schrieb Don Slutz: > On 09/10/12 09:04, Igor Mammedov wrote: >> But question unrelated to this patch is still stand if ia64 is valid >> bit for >> 01.EDX[30]? >> >> > Intel® Processor Identification > and the CPUID Instruction > Application Note 485 > January 2006 > > Order Number: 241618-030 > > ... > > Updated Table 3-5 to include the feature flag definition (EDX[30]) for > IA64 capabilities. > ... > 30 IA64 IA64 Capabilities The processor is a member of the Intel® > Itanium® processor family > and currently operating in IA32 emulation mode. > > --------------- > > Says that it is. Along with http://en.wikipedia.org/wiki/CPUID and > http://www.sandpile.org/x86/cpuid.htm#level_0000_0001h (IA-64) Don't those semantics contradict the use in qemu-system-x86_64 or qemu-system-i386 rather than qemu-system-ia64 then? We don't model ia64 CPUs here (just like we don't model ppc64 CPUs in ppc) so the flag could never become 1 IIUC. Andreas > But the newest version I found (241618-037, January 2011) is back to > Reserved. > > > -Don Slutz
On Mon, Sep 10, 2012 at 03:04:30PM +0200, Igor Mammedov wrote: > On Mon, 10 Sep 2012 14:31:49 +0200 > Igor Mammedov <imammedo@redhat.com> wrote: > > > On Mon, 10 Sep 2012 14:18:38 +0200 > > Igor Mammedov <imammedo@redhat.com> wrote: > > > > > On Wed, 5 Sep 2012 17:41:10 -0300 > > > Eduardo Habkost <ehabkost@redhat.com> wrote: > > > > > > > Those models are maintained by QEMU and may require compatibility code > > > > to be added when making some changes. Keeping the data in the C source > > > > code should make it simpler to handle those details. > > > > > > > > Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> > > > > --- > > > > sysconfigs/target/cpus-x86_64.conf | 129 +--------------------- > > > > target-i386/cpu.c | 219 > > > > +++++++++++++++++++++++++++++++++++++ 2 files changed, 220 > > > > insertions(+), 128 deletions(-) > > > > > > > > diff --git a/sysconfigs/target/cpus-x86_64.conf > > > > b/sysconfigs/target/cpus-x86_64.conf index cee0ea9..3902189 100644 > > > > --- a/sysconfigs/target/cpus-x86_64.conf > > > > +++ b/sysconfigs/target/cpus-x86_64.conf > > > > @@ -1,128 +1 @@ > > > > -# x86 CPU MODELS > > > > - > > > > -[cpudef] > > > > - name = "Conroe" > > > > - level = "2" > > > > - vendor = "GenuineIntel" > > > > - family = "6" > > > > - model = "2" > > > > - stepping = "3" > > > > - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr > > > > sep apic cx8 mce pae msr tsc pse de fpu" > > > > - feature_ecx = "ssse3 sse3" > > > > - extfeature_edx = "i64 xd syscall" > > > ... > > > > + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | > > > > CPUID_EXT2_SYSCALL, > > > Silent fix, replacing i64 with CPUID_EXT2_LM > > > looks like "i64" is mistake and never worked. In Intel & AMD cpuid guides > > Actually it works when setting feature fields because it uses > > setfeatures(), however setting i64 will set wrong bit if it's set using > > add_flagname_to_bitmaps() > I'm wrong, and sorry for noise. I mixed up ia64 from feature_name with i64 > from ext2_feature_name. > > But question unrelated to this patch is still stand if ia64 is valid bit for > 01.EDX[30]? It is reserved on IA-32 and Intel-64/AMD64, but it has a name/meaning, already[1]. The name of that bit is in the table, but it's harmless (and useless) because both KVM and TCG modes disable it automatically (and -cpu check/enforce should warn about it not being supported by the host). [1] Linux recognizes it as X86_FEATURE_IA64/"ia64". Itanium SDM documents it as: "30 Processor based on the Intel Itanium architecture "The processor is based on the Intel Itanium architecture and is capable of executing the Intel Itanium instruction set. IA-32 application level software MUST also check with the running operating system to see if the system can also support Itanium architecture-based code before switching to the Intel Itanium instruction set."
On Mon, Sep 10, 2012 at 04:58:39PM +0200, Andreas Färber wrote: > Am 10.09.2012 16:50, schrieb Don Slutz: > > On 09/10/12 09:04, Igor Mammedov wrote: > >> But question unrelated to this patch is still stand if ia64 is valid > >> bit for > >> 01.EDX[30]? > >> > >> > > Intel® Processor Identification > > and the CPUID Instruction > > Application Note 485 > > January 2006 > > > > Order Number: 241618-030 > > > > ... > > > > Updated Table 3-5 to include the feature flag definition (EDX[30]) for > > IA64 capabilities. > > ... > > 30 IA64 IA64 Capabilities The processor is a member of the Intel® > > Itanium® processor family > > and currently operating in IA32 emulation mode. > > > > --------------- > > > > Says that it is. Along with http://en.wikipedia.org/wiki/CPUID and > > http://www.sandpile.org/x86/cpuid.htm#level_0000_0001h (IA-64) > > Don't those semantics contradict the use in qemu-system-x86_64 or > qemu-system-i386 rather than qemu-system-ia64 then? We don't model ia64 > CPUs here (just like we don't model ppc64 CPUs in ppc) so the flag could > never become 1 IIUC. Correct, and the bit is always filtered out on both TCG and KVM modes. The name is in the table because we know the name/meaning of that feature bit, but it's impossible to enable it. That said, I don't mind removing it from the table just to avoid confusion, but I also wouldn't mind keeping it (as it's harmless).
Am 10.09.2012 17:07, schrieb Eduardo Habkost: > On Mon, Sep 10, 2012 at 04:58:39PM +0200, Andreas Färber wrote: >> Am 10.09.2012 16:50, schrieb Don Slutz: >>> On 09/10/12 09:04, Igor Mammedov wrote: >>>> But question unrelated to this patch is still stand if ia64 is valid >>>> bit for >>>> 01.EDX[30]? >>>> >>>> >>> Intel® Processor Identification >>> and the CPUID Instruction >>> Application Note 485 >>> January 2006 >>> >>> Order Number: 241618-030 >>> >>> ... >>> >>> Updated Table 3-5 to include the feature flag definition (EDX[30]) for >>> IA64 capabilities. >>> ... >>> 30 IA64 IA64 Capabilities The processor is a member of the Intel® >>> Itanium® processor family >>> and currently operating in IA32 emulation mode. >>> >>> --------------- >>> >>> Says that it is. Along with http://en.wikipedia.org/wiki/CPUID and >>> http://www.sandpile.org/x86/cpuid.htm#level_0000_0001h (IA-64) >> >> Don't those semantics contradict the use in qemu-system-x86_64 or >> qemu-system-i386 rather than qemu-system-ia64 then? We don't model ia64 >> CPUs here (just like we don't model ppc64 CPUs in ppc) so the flag could >> never become 1 IIUC. > > Correct, and the bit is always filtered out on both TCG and KVM modes. > The name is in the table because we know the name/meaning of that > feature bit, but it's impossible to enable it. > > That said, I don't mind removing it from the table just to avoid > confusion, but I also wouldn't mind keeping it (as it's harmless). No objections from my side against having it for informational purpose. Andreas
On 09/10/12 09:40, Igor Mammedov wrote: > On Wed, 5 Sep 2012 17:41:10 -0300 > Eduardo Habkost <ehabkost@redhat.com> wrote: > >> Those models are maintained by QEMU and may require compatibility code >> to be added when making some changes. Keeping the data in the C source >> code should make it simpler to handle those details. >> >> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> >> --- >> sysconfigs/target/cpus-x86_64.conf | 129 +--------------------- >> target-i386/cpu.c | 219 >> +++++++++++++++++++++++++++++++++++++ 2 files changed, 220 insertions(+), >> 128 deletions(-) >> >> diff --git a/sysconfigs/target/cpus-x86_64.conf >> b/sysconfigs/target/cpus-x86_64.conf index cee0ea9..3902189 100644 >> --- a/sysconfigs/target/cpus-x86_64.conf >> +++ b/sysconfigs/target/cpus-x86_64.conf >> @@ -1,128 +1 @@ >> -# x86 CPU MODELS >> - >> -[cpudef] >> - name = "Conroe" >> - level = "2" >> - vendor = "GenuineIntel" >> - family = "6" >> - model = "2" >> - stepping = "3" >> - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr >> sep apic cx8 mce pae msr tsc pse de fpu" >> - feature_ecx = "ssse3 sse3" >> - extfeature_edx = "i64 xd syscall" >> - extfeature_ecx = "lahf_lm" >> - xlevel = "0x8000000A" >> - model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)" >> - >> -[cpudef] >> - name = "Penryn" >> - level = "2" >> - vendor = "GenuineIntel" >> - family = "6" >> - model = "2" >> - stepping = "3" >> - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr >> sep apic cx8 mce pae msr tsc pse de fpu" >> - feature_ecx = "sse4.1 cx16 ssse3 sse3" >> - extfeature_edx = "i64 xd syscall" >> - extfeature_ecx = "lahf_lm" >> - xlevel = "0x8000000A" >> - model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)" >> - >> -[cpudef] >> - name = "Nehalem" >> - level = "2" >> - vendor = "GenuineIntel" >> - family = "6" >> - model = "2" >> - stepping = "3" >> - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr >> sep apic cx8 mce pae msr tsc pse de fpu" >> - feature_ecx = "popcnt sse4.2 sse4.1 cx16 ssse3 sse3" >> - extfeature_edx = "i64 syscall xd" >> - extfeature_ecx = "lahf_lm" >> - xlevel = "0x8000000A" >> - model_id = "Intel Core i7 9xx (Nehalem Class Core i7)" >> - >> -[cpudef] >> - name = "Westmere" >> - level = "11" >> - vendor = "GenuineIntel" >> - family = "6" >> - model = "44" >> - stepping = "1" >> - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr >> sep apic cx8 mce pae msr tsc pse de fpu" >> - feature_ecx = "aes popcnt sse4.2 sse4.1 cx16 ssse3 sse3" >> - extfeature_edx = "i64 syscall xd" >> - extfeature_ecx = "lahf_lm" >> - xlevel = "0x8000000A" >> - model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)" >> - >> -[cpudef] >> - name = "SandyBridge" >> - level = "0xd" >> - vendor = "GenuineIntel" >> - family = "6" >> - model = "42" >> - stepping = "1" >> - feature_edx = " sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr >> sep apic cx8 mce pae msr tsc pse de fpu" >> - feature_ecx = "avx xsave aes tsc-deadline popcnt x2apic sse4.2 sse4.1 >> cx16 ssse3 pclmulqdq sse3" >> - extfeature_edx = "i64 rdtscp nx syscall " >> - extfeature_ecx = "lahf_lm" >> - xlevel = "0x8000000A" >> - model_id = "Intel Xeon E312xx (Sandy Bridge)" >> - >> -[cpudef] >> - name = "Opteron_G1" >> - level = "5" >> - vendor = "AuthenticAMD" >> - family = "15" >> - model = "6" >> - stepping = "1" >> - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr >> sep apic cx8 mce pae msr tsc pse de fpu" >> - feature_ecx = "sse3" >> - extfeature_edx = "lm fxsr mmx nx pse36 pat cmov mca pge mtrr syscall >> apic cx8 mce pae msr tsc pse de fpu" >> - extfeature_ecx = " " >> - xlevel = "0x80000008" >> - model_id = "AMD Opteron 240 (Gen 1 Class Opteron)" >> - >> -[cpudef] >> - name = "Opteron_G2" >> - level = "5" >> - vendor = "AuthenticAMD" >> - family = "15" >> - model = "6" >> - stepping = "1" >> - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr >> sep apic cx8 mce pae msr tsc pse de fpu" >> - feature_ecx = "cx16 sse3" >> - extfeature_edx = "lm rdtscp fxsr mmx nx pse36 pat cmov mca pge mtrr >> syscall apic cx8 mce pae msr tsc pse de fpu" >> - extfeature_ecx = "svm lahf_lm" >> - xlevel = "0x80000008" >> - model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)" >> - >> -[cpudef] >> - name = "Opteron_G3" >> - level = "5" >> - vendor = "AuthenticAMD" >> - family = "15" >> - model = "6" >> - stepping = "1" >> - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr >> sep apic cx8 mce pae msr tsc pse de fpu" >> - feature_ecx = "popcnt cx16 monitor sse3" >> - extfeature_edx = "lm rdtscp fxsr mmx nx pse36 pat cmov mca pge mtrr >> syscall apic cx8 mce pae msr tsc pse de fpu" >> - extfeature_ecx = "misalignsse sse4a abm svm lahf_lm" >> - xlevel = "0x80000008" >> - model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)" >> - >> -[cpudef] >> - name = "Opteron_G4" >> - level = "0xd" >> - vendor = "AuthenticAMD" >> - family = "21" >> - model = "1" >> - stepping = "2" >> - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr >> sep apic cx8 mce pae msr tsc pse de fpu" >> - feature_ecx = "avx xsave aes popcnt sse4.2 sse4.1 cx16 ssse3 pclmulqdq >> sse3" >> - extfeature_edx = "lm rdtscp pdpe1gb fxsr mmx nx pse36 pat cmov mca pge >> mtrr syscall apic cx8 mce pae msr tsc pse de fpu" >> - extfeature_ecx = " fma4 xop 3dnowprefetch misalignsse sse4a abm svm >> lahf_lm" >> - xlevel = "0x8000001A" >> - model_id = "AMD Opteron 62xx class CPU" >> - >> +# The CPU models from this file are now built-in in the QEMU source code >> diff --git a/target-i386/cpu.c b/target-i386/cpu.c >> index d2af0ff..73302d8 100644 >> --- a/target-i386/cpu.c >> +++ b/target-i386/cpu.c >> @@ -490,6 +490,225 @@ static x86_def_t builtin_x86_defs[] = { >> .xlevel = 0x8000000A, >> .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", >> }, >> + { >> + .name = "Conroe", >> + .level = 2, >> + .vendor1 = CPUID_VENDOR_INTEL_1, >> + .vendor2 = CPUID_VENDOR_INTEL_2, >> + .vendor3 = CPUID_VENDOR_INTEL_3, >> + .family = 6, >> + .model = 2, >> + .stepping = 3, >> + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | >> + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | >> CPUID_MCA | >> + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | >> + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | >> + CPUID_DE | CPUID_FP87, >> + .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, >> + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | >> CPUID_EXT2_SYSCALL, >> + .ext3_features = CPUID_EXT3_LAHF_LM, >> + .xlevel = 0x8000000A, >> + .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", >> + }, >> + { >> + .name = "Penryn", >> + .level = 2, >> + .vendor1 = CPUID_VENDOR_INTEL_1, >> + .vendor2 = CPUID_VENDOR_INTEL_2, >> + .vendor3 = CPUID_VENDOR_INTEL_3, >> + .family = 6, >> + .model = 2, >> + .stepping = 3, >> + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | >> + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | >> CPUID_MCA | >> + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | >> + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | >> + CPUID_DE | CPUID_FP87, >> + .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 >> | >> + CPUID_EXT_SSE3, >> + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | >> CPUID_EXT2_SYSCALL, >> + .ext3_features = CPUID_EXT3_LAHF_LM, >> + .xlevel = 0x8000000A, >> + .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", >> + }, >> + { >> + .name = "Nehalem", >> + .level = 2, >> + .vendor1 = CPUID_VENDOR_INTEL_1, >> + .vendor2 = CPUID_VENDOR_INTEL_2, >> + .vendor3 = CPUID_VENDOR_INTEL_3, >> + .family = 6, >> + .model = 2, >> + .stepping = 3, >> + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | >> + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | >> CPUID_MCA | >> + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | >> + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | >> + CPUID_DE | CPUID_FP87, >> + .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | >> CPUID_EXT_SSE41 | >> + CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, >> + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | >> CPUID_EXT2_NX, >> + .ext3_features = CPUID_EXT3_LAHF_LM, >> + .xlevel = 0x8000000A, >> + .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", >> + }, >> + { >> + .name = "Westmere", >> + .level = 11, >> + .vendor1 = CPUID_VENDOR_INTEL_1, >> + .vendor2 = CPUID_VENDOR_INTEL_2, >> + .vendor3 = CPUID_VENDOR_INTEL_3, >> + .family = 6, >> + .model = 44, >> + .stepping = 1, >> + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | >> + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | >> CPUID_MCA | >> + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | >> + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | >> + CPUID_DE | CPUID_FP87, >> + .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 >> | >> + CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | >> + CPUID_EXT_SSE3, >> + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | >> CPUID_EXT2_NX, >> + .ext3_features = CPUID_EXT3_LAHF_LM, >> + .xlevel = 0x8000000A, >> + .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", >> + }, >> + { >> + .name = "SandyBridge", >> + .level = 0xd, >> + .vendor1 = CPUID_VENDOR_INTEL_1, >> + .vendor2 = CPUID_VENDOR_INTEL_2, >> + .vendor3 = CPUID_VENDOR_INTEL_3, >> + .family = 6, >> + .model = 42, >> + .stepping = 1, >> + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | >> + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | >> CPUID_MCA | >> + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | >> + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | >> + CPUID_DE | CPUID_FP87, >> + .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | >> + CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | >> + CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | >> + CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | >> + CPUID_EXT_SSE3, >> + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX >> | >> + CPUID_EXT2_SYSCALL, >> + .ext3_features = CPUID_EXT3_LAHF_LM, >> + .xlevel = 0x8000000A, >> + .model_id = "Intel Xeon E312xx (Sandy Bridge)", >> + }, >> + { >> + .name = "Opteron_G1", >> + .level = 5, >> + .vendor1 = CPUID_VENDOR_AMD_1, >> + .vendor2 = CPUID_VENDOR_AMD_2, >> + .vendor3 = CPUID_VENDOR_AMD_3, >> + .family = 15, >> + .model = 6, >> + .stepping = 1, >> + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | >> + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | >> CPUID_MCA | >> + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | >> + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | >> + CPUID_DE | CPUID_FP87, >> + .ext_features = CPUID_EXT_SSE3, >> + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX | >> + CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT | >> + CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE | >> + CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC | >> + CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | >> CPUID_EXT2_MSR | >> + CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | >> CPUID_EXT2_FPU, >> + .xlevel = 0x80000008, >> + .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", >> + }, >> + { >> + .name = "Opteron_G2", >> + .level = 5, >> + .vendor1 = CPUID_VENDOR_AMD_1, >> + .vendor2 = CPUID_VENDOR_AMD_2, >> + .vendor3 = CPUID_VENDOR_AMD_3, >> + .family = 15, >> + .model = 6, >> + .stepping = 1, >> + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | >> + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | >> CPUID_MCA | >> + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | >> + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | >> + CPUID_DE | CPUID_FP87, >> + .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3, >> + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | >> CPUID_EXT2_FXSR | >> + CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 | >> + CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA | >> + CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | >> + CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE | >> + CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | >> CPUID_EXT2_PSE | >> + CPUID_EXT2_DE | CPUID_EXT2_FPU, >> + .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, >> + .xlevel = 0x80000008, >> + .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", >> + }, >> + { >> + .name = "Opteron_G3", >> + .level = 5, >> + .vendor1 = CPUID_VENDOR_AMD_1, >> + .vendor2 = CPUID_VENDOR_AMD_2, >> + .vendor3 = CPUID_VENDOR_AMD_3, >> + .family = 15, >> + .model = 6, >> + .stepping = 1, >> + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | >> + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | >> CPUID_MCA | >> + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | >> + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | >> + CPUID_DE | CPUID_FP87, >> + .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 | >> CPUID_EXT_MONITOR | >> + CPUID_EXT_SSE3, >> + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | >> CPUID_EXT2_FXSR | >> + CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 | >> + CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA | >> + CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | >> + CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE | >> + CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | >> CPUID_EXT2_PSE | >> + CPUID_EXT2_DE | CPUID_EXT2_FPU, >> + .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | >> + CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, >> + .xlevel = 0x80000008, >> + .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", >> + }, >> + { >> + .name = "Opteron_G4", >> + .level = 0xd, >> + .vendor1 = CPUID_VENDOR_AMD_1, >> + .vendor2 = CPUID_VENDOR_AMD_2, >> + .vendor3 = CPUID_VENDOR_AMD_3, >> + .family = 21, >> + .model = 1, >> + .stepping = 2, >> + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | >> + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | >> CPUID_MCA | >> + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | >> + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | >> + CPUID_DE | CPUID_FP87, >> + .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | >> + CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | >> + CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | >> + CPUID_EXT_SSE3, >> + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | >> + CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX | >> + CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT | >> + CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE | >> + CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC | >> + CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | >> CPUID_EXT2_MSR | >> + CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | >> CPUID_EXT2_FPU, >> + .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | >> + CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | >> + CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | >> + CPUID_EXT3_LAHF_LM, >> + .xlevel = 0x8000001A, >> + .model_id = "AMD Opteron 62xx class CPU", >> + }, >> }; >> >> static int cpu_x86_fill_model_id(char *str) > Reviewed-by: Igor Mammedov <imammedo@redhat.com> > Reviewed-by: Don Slutz <Don@CloudSwitch.com>
diff --git a/sysconfigs/target/cpus-x86_64.conf b/sysconfigs/target/cpus-x86_64.conf index cee0ea9..3902189 100644 --- a/sysconfigs/target/cpus-x86_64.conf +++ b/sysconfigs/target/cpus-x86_64.conf @@ -1,128 +1 @@ -# x86 CPU MODELS - -[cpudef] - name = "Conroe" - level = "2" - vendor = "GenuineIntel" - family = "6" - model = "2" - stepping = "3" - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu" - feature_ecx = "ssse3 sse3" - extfeature_edx = "i64 xd syscall" - extfeature_ecx = "lahf_lm" - xlevel = "0x8000000A" - model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)" - -[cpudef] - name = "Penryn" - level = "2" - vendor = "GenuineIntel" - family = "6" - model = "2" - stepping = "3" - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu" - feature_ecx = "sse4.1 cx16 ssse3 sse3" - extfeature_edx = "i64 xd syscall" - extfeature_ecx = "lahf_lm" - xlevel = "0x8000000A" - model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)" - -[cpudef] - name = "Nehalem" - level = "2" - vendor = "GenuineIntel" - family = "6" - model = "2" - stepping = "3" - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu" - feature_ecx = "popcnt sse4.2 sse4.1 cx16 ssse3 sse3" - extfeature_edx = "i64 syscall xd" - extfeature_ecx = "lahf_lm" - xlevel = "0x8000000A" - model_id = "Intel Core i7 9xx (Nehalem Class Core i7)" - -[cpudef] - name = "Westmere" - level = "11" - vendor = "GenuineIntel" - family = "6" - model = "44" - stepping = "1" - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu" - feature_ecx = "aes popcnt sse4.2 sse4.1 cx16 ssse3 sse3" - extfeature_edx = "i64 syscall xd" - extfeature_ecx = "lahf_lm" - xlevel = "0x8000000A" - model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)" - -[cpudef] - name = "SandyBridge" - level = "0xd" - vendor = "GenuineIntel" - family = "6" - model = "42" - stepping = "1" - feature_edx = " sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu" - feature_ecx = "avx xsave aes tsc-deadline popcnt x2apic sse4.2 sse4.1 cx16 ssse3 pclmulqdq sse3" - extfeature_edx = "i64 rdtscp nx syscall " - extfeature_ecx = "lahf_lm" - xlevel = "0x8000000A" - model_id = "Intel Xeon E312xx (Sandy Bridge)" - -[cpudef] - name = "Opteron_G1" - level = "5" - vendor = "AuthenticAMD" - family = "15" - model = "6" - stepping = "1" - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu" - feature_ecx = "sse3" - extfeature_edx = "lm fxsr mmx nx pse36 pat cmov mca pge mtrr syscall apic cx8 mce pae msr tsc pse de fpu" - extfeature_ecx = " " - xlevel = "0x80000008" - model_id = "AMD Opteron 240 (Gen 1 Class Opteron)" - -[cpudef] - name = "Opteron_G2" - level = "5" - vendor = "AuthenticAMD" - family = "15" - model = "6" - stepping = "1" - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu" - feature_ecx = "cx16 sse3" - extfeature_edx = "lm rdtscp fxsr mmx nx pse36 pat cmov mca pge mtrr syscall apic cx8 mce pae msr tsc pse de fpu" - extfeature_ecx = "svm lahf_lm" - xlevel = "0x80000008" - model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)" - -[cpudef] - name = "Opteron_G3" - level = "5" - vendor = "AuthenticAMD" - family = "15" - model = "6" - stepping = "1" - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu" - feature_ecx = "popcnt cx16 monitor sse3" - extfeature_edx = "lm rdtscp fxsr mmx nx pse36 pat cmov mca pge mtrr syscall apic cx8 mce pae msr tsc pse de fpu" - extfeature_ecx = "misalignsse sse4a abm svm lahf_lm" - xlevel = "0x80000008" - model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)" - -[cpudef] - name = "Opteron_G4" - level = "0xd" - vendor = "AuthenticAMD" - family = "21" - model = "1" - stepping = "2" - feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu" - feature_ecx = "avx xsave aes popcnt sse4.2 sse4.1 cx16 ssse3 pclmulqdq sse3" - extfeature_edx = "lm rdtscp pdpe1gb fxsr mmx nx pse36 pat cmov mca pge mtrr syscall apic cx8 mce pae msr tsc pse de fpu" - extfeature_ecx = " fma4 xop 3dnowprefetch misalignsse sse4a abm svm lahf_lm" - xlevel = "0x8000001A" - model_id = "AMD Opteron 62xx class CPU" - +# The CPU models from this file are now built-in in the QEMU source code diff --git a/target-i386/cpu.c b/target-i386/cpu.c index d2af0ff..73302d8 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -490,6 +490,225 @@ static x86_def_t builtin_x86_defs[] = { .xlevel = 0x8000000A, .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", }, + { + .name = "Conroe", + .level = 2, + .vendor1 = CPUID_VENDOR_INTEL_1, + .vendor2 = CPUID_VENDOR_INTEL_2, + .vendor3 = CPUID_VENDOR_INTEL_3, + .family = 6, + .model = 2, + .stepping = 3, + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | + CPUID_DE | CPUID_FP87, + .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, + .ext3_features = CPUID_EXT3_LAHF_LM, + .xlevel = 0x8000000A, + .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", + }, + { + .name = "Penryn", + .level = 2, + .vendor1 = CPUID_VENDOR_INTEL_1, + .vendor2 = CPUID_VENDOR_INTEL_2, + .vendor3 = CPUID_VENDOR_INTEL_3, + .family = 6, + .model = 2, + .stepping = 3, + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | + CPUID_DE | CPUID_FP87, + .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | + CPUID_EXT_SSE3, + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, + .ext3_features = CPUID_EXT3_LAHF_LM, + .xlevel = 0x8000000A, + .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", + }, + { + .name = "Nehalem", + .level = 2, + .vendor1 = CPUID_VENDOR_INTEL_1, + .vendor2 = CPUID_VENDOR_INTEL_2, + .vendor3 = CPUID_VENDOR_INTEL_3, + .family = 6, + .model = 2, + .stepping = 3, + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | + CPUID_DE | CPUID_FP87, + .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | + CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, + .ext3_features = CPUID_EXT3_LAHF_LM, + .xlevel = 0x8000000A, + .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", + }, + { + .name = "Westmere", + .level = 11, + .vendor1 = CPUID_VENDOR_INTEL_1, + .vendor2 = CPUID_VENDOR_INTEL_2, + .vendor3 = CPUID_VENDOR_INTEL_3, + .family = 6, + .model = 44, + .stepping = 1, + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | + CPUID_DE | CPUID_FP87, + .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | + CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | + CPUID_EXT_SSE3, + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, + .ext3_features = CPUID_EXT3_LAHF_LM, + .xlevel = 0x8000000A, + .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", + }, + { + .name = "SandyBridge", + .level = 0xd, + .vendor1 = CPUID_VENDOR_INTEL_1, + .vendor2 = CPUID_VENDOR_INTEL_2, + .vendor3 = CPUID_VENDOR_INTEL_3, + .family = 6, + .model = 42, + .stepping = 1, + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | + CPUID_DE | CPUID_FP87, + .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | + CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | + CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | + CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | + CPUID_EXT_SSE3, + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | + CPUID_EXT2_SYSCALL, + .ext3_features = CPUID_EXT3_LAHF_LM, + .xlevel = 0x8000000A, + .model_id = "Intel Xeon E312xx (Sandy Bridge)", + }, + { + .name = "Opteron_G1", + .level = 5, + .vendor1 = CPUID_VENDOR_AMD_1, + .vendor2 = CPUID_VENDOR_AMD_2, + .vendor3 = CPUID_VENDOR_AMD_3, + .family = 15, + .model = 6, + .stepping = 1, + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | + CPUID_DE | CPUID_FP87, + .ext_features = CPUID_EXT_SSE3, + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX | + CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT | + CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE | + CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC | + CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR | + CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU, + .xlevel = 0x80000008, + .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", + }, + { + .name = "Opteron_G2", + .level = 5, + .vendor1 = CPUID_VENDOR_AMD_1, + .vendor2 = CPUID_VENDOR_AMD_2, + .vendor3 = CPUID_VENDOR_AMD_3, + .family = 15, + .model = 6, + .stepping = 1, + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | + CPUID_DE | CPUID_FP87, + .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3, + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR | + CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 | + CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA | + CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | + CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE | + CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE | + CPUID_EXT2_DE | CPUID_EXT2_FPU, + .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, + .xlevel = 0x80000008, + .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", + }, + { + .name = "Opteron_G3", + .level = 5, + .vendor1 = CPUID_VENDOR_AMD_1, + .vendor2 = CPUID_VENDOR_AMD_2, + .vendor3 = CPUID_VENDOR_AMD_3, + .family = 15, + .model = 6, + .stepping = 1, + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | + CPUID_DE | CPUID_FP87, + .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | + CPUID_EXT_SSE3, + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR | + CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 | + CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA | + CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | + CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE | + CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE | + CPUID_EXT2_DE | CPUID_EXT2_FPU, + .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | + CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, + .xlevel = 0x80000008, + .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", + }, + { + .name = "Opteron_G4", + .level = 0xd, + .vendor1 = CPUID_VENDOR_AMD_1, + .vendor2 = CPUID_VENDOR_AMD_2, + .vendor3 = CPUID_VENDOR_AMD_3, + .family = 21, + .model = 1, + .stepping = 2, + .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | + CPUID_DE | CPUID_FP87, + .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | + CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | + CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | + CPUID_EXT_SSE3, + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | + CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX | + CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT | + CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE | + CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC | + CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR | + CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU, + .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | + CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | + CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | + CPUID_EXT3_LAHF_LM, + .xlevel = 0x8000001A, + .model_id = "AMD Opteron 62xx class CPU", + }, }; static int cpu_x86_fill_model_id(char *str)
Those models are maintained by QEMU and may require compatibility code to be added when making some changes. Keeping the data in the C source code should make it simpler to handle those details. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> --- sysconfigs/target/cpus-x86_64.conf | 129 +--------------------- target-i386/cpu.c | 219 +++++++++++++++++++++++++++++++++++++ 2 files changed, 220 insertions(+), 128 deletions(-)