From patchwork Tue Sep 4 20:37:19 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Blue Swirl X-Patchwork-Id: 181672 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 5A7DB2C00B1 for ; Wed, 5 Sep 2012 06:37:41 +1000 (EST) Received: from localhost ([::1]:59655 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1T8zsQ-0004ip-W6 for incoming@patchwork.ozlabs.org; Tue, 04 Sep 2012 16:37:38 -0400 Received: from eggs.gnu.org ([208.118.235.92]:46364) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1T8zsI-0004hb-Hh for qemu-devel@nongnu.org; Tue, 04 Sep 2012 16:37:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1T8zsH-0006lc-96 for qemu-devel@nongnu.org; Tue, 04 Sep 2012 16:37:30 -0400 Received: from mail-ey0-f173.google.com ([209.85.215.173]:55744) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1T8zsG-0006lV-Sj for qemu-devel@nongnu.org; Tue, 04 Sep 2012 16:37:29 -0400 Received: by eaac13 with SMTP id c13so2089176eaa.4 for ; Tue, 04 Sep 2012 13:37:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=T6mwIUXoJBOTOcrI845E905IBA4fslQM9bS2/lvs8so=; b=Nj2dzmVlfi+QjXB4XaAl1FXSPEcXnzktpWjs56lyrTwi1HH+H1CAvWS0BAkWgZJlId Xv31ebWQ+jP/kQpnUvVS5VnooQm+E5MdD4xeE8jk8gB5IURNbzHuifufj05LpoxkKw4i VBshYwHFdi5PvQ3oLKd4ODf5bQq9aUm0AHdIwha/u4gLhe5I1KuhM2CKJ2SGNvtxiTNI gh10ypMr90kKrP0c5mnc37siKD2mURkJzQ2gYgyUsMvXnfn2QcRmBVmzzVOfKjaf9loq P/ww9BplIGgL3uko6fKJ/hd4RjnCNYc6uS0K8qBgUlU/ne8jW6uzXOCeddK1aKQVC+1k 6kiA== Received: by 10.14.198.65 with SMTP id u41mr28084068een.22.1346791048015; Tue, 04 Sep 2012 13:37:28 -0700 (PDT) Received: from localhost.localdomain ([2001:5c0:1115:ba00:a585:1a17:fc72:95e4]) by mx.google.com with ESMTPS id 45sm48218801eed.17.2012.09.04.13.37.23 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 04 Sep 2012 13:37:25 -0700 (PDT) From: Blue Swirl To: qemu-devel@nongnu.org Date: Tue, 4 Sep 2012 20:37:19 +0000 Message-Id: X-Mailer: git-send-email 1.7.2.5 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.215.173 Cc: blauwirbel@gmail.com, Peter Maydell , Paul Brook Subject: [Qemu-devel] [PATCH 1/3] target-arm: convert void helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add an explicit CPUState parameter instead of relying on AREG0. For easier review, convert only op helpers which don't return any value. Signed-off-by: Blue Swirl Reviewed-by: Peter Maydell --- target-arm/helper.h | 8 ++++---- target-arm/op_helper.c | 20 ++++++++++---------- target-arm/translate.c | 8 ++++---- 3 files changed, 18 insertions(+), 18 deletions(-) diff --git a/target-arm/helper.h b/target-arm/helper.h index 21e9cfe..106aacd 100644 --- a/target-arm/helper.h +++ b/target-arm/helper.h @@ -50,10 +50,10 @@ DEF_HELPER_2(usad8, i32, i32, i32) DEF_HELPER_1(logicq_cc, i32, i64) DEF_HELPER_3(sel_flags, i32, i32, i32, i32) -DEF_HELPER_1(exception, void, i32) -DEF_HELPER_0(wfi, void) +DEF_HELPER_2(exception, void, env, i32) +DEF_HELPER_1(wfi, void, env) -DEF_HELPER_2(cpsr_write, void, i32, i32) +DEF_HELPER_3(cpsr_write, void, env, i32, i32) DEF_HELPER_0(cpsr_read, i32) DEF_HELPER_3(v7m_msr, void, env, i32, i32) @@ -68,7 +68,7 @@ DEF_HELPER_2(get_r13_banked, i32, env, i32) DEF_HELPER_3(set_r13_banked, void, env, i32, i32) DEF_HELPER_1(get_user_reg, i32, i32) -DEF_HELPER_2(set_user_reg, void, i32, i32) +DEF_HELPER_3(set_user_reg, void, env, i32, i32) DEF_HELPER_1(vfp_get_fpscr, i32, env) DEF_HELPER_2(vfp_set_fpscr, void, env, i32) diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index d77bfab..b1adce3 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -23,7 +23,7 @@ #define SIGNBIT (uint32_t)0x80000000 #define SIGNBIT64 ((uint64_t)1 << 63) -static void raise_exception(int tt) +static void raise_exception(CPUARMState *env, int tt) { env->exception_index = tt; cpu_loop_exit(env); @@ -93,7 +93,7 @@ void tlb_fill(CPUARMState *env1, target_ulong addr, int is_write, int mmu_idx, cpu_restore_state(tb, env, retaddr); } } - raise_exception(env->exception_index); + raise_exception(env, env->exception_index); } env = saved_env; } @@ -230,14 +230,14 @@ uint32_t HELPER(usat16)(uint32_t x, uint32_t shift) return res; } -void HELPER(wfi)(void) +void HELPER(wfi)(CPUARMState *env) { env->exception_index = EXCP_HLT; env->halted = 1; cpu_loop_exit(env); } -void HELPER(exception)(uint32_t excp) +void HELPER(exception)(CPUARMState *env, uint32_t excp) { env->exception_index = excp; cpu_loop_exit(env); @@ -248,7 +248,7 @@ uint32_t HELPER(cpsr_read)(void) return cpsr_read(env) & ~CPSR_EXEC; } -void HELPER(cpsr_write)(uint32_t val, uint32_t mask) +void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask) { cpsr_write(env, val, mask); } @@ -271,7 +271,7 @@ uint32_t HELPER(get_user_reg)(uint32_t regno) return val; } -void HELPER(set_user_reg)(uint32_t regno, uint32_t val) +void HELPER(set_user_reg)(CPUARMState *env, uint32_t regno, uint32_t val) { if (regno == 13) { env->banked_r13[0] = val; @@ -290,7 +290,7 @@ void HELPER(set_cp_reg)(CPUARMState *env, void *rip, uint32_t value) const ARMCPRegInfo *ri = rip; int excp = ri->writefn(env, ri, value); if (excp) { - raise_exception(excp); + raise_exception(env, excp); } } @@ -300,7 +300,7 @@ uint32_t HELPER(get_cp_reg)(CPUARMState *env, void *rip) uint64_t value; int excp = ri->readfn(env, ri, &value); if (excp) { - raise_exception(excp); + raise_exception(env, excp); } return value; } @@ -310,7 +310,7 @@ void HELPER(set_cp_reg64)(CPUARMState *env, void *rip, uint64_t value) const ARMCPRegInfo *ri = rip; int excp = ri->writefn(env, ri, value); if (excp) { - raise_exception(excp); + raise_exception(env, excp); } } @@ -320,7 +320,7 @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip) uint64_t value; int excp = ri->readfn(env, ri, &value); if (excp) { - raise_exception(excp); + raise_exception(env, excp); } return value; } diff --git a/target-arm/translate.c b/target-arm/translate.c index edef79a..6f651d9 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -199,7 +199,7 @@ static void store_reg(DisasContext *s, int reg, TCGv var) static inline void gen_set_cpsr(TCGv var, uint32_t mask) { TCGv tmp_mask = tcg_const_i32(mask); - gen_helper_cpsr_write(var, tmp_mask); + gen_helper_cpsr_write(cpu_env, var, tmp_mask); tcg_temp_free_i32(tmp_mask); } /* Set NZCV flags from the high 4 bits of var. */ @@ -209,7 +209,7 @@ static void gen_exception(int excp) { TCGv tmp = tcg_temp_new_i32(); tcg_gen_movi_i32(tmp, excp); - gen_helper_exception(tmp); + gen_helper_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); } @@ -7719,7 +7719,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s) tmp = gen_ld32(addr, IS_USER(s)); if (user) { tmp2 = tcg_const_i32(i); - gen_helper_set_user_reg(tmp2, tmp); + gen_helper_set_user_reg(cpu_env, tmp2, tmp); tcg_temp_free_i32(tmp2); tcg_temp_free_i32(tmp); } else if (i == rn) { @@ -9913,7 +9913,7 @@ static inline void gen_intermediate_code_internal(CPUARMState *env, /* nothing more to generate */ break; case DISAS_WFI: - gen_helper_wfi(); + gen_helper_wfi(cpu_env); break; case DISAS_SWI: gen_exception(EXCP_SWI);