From patchwork Tue Sep 4 09:01:25 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [-V7, 08/12] arch/powerpc: Make some of the PGTABLE_RANGE dependency explicit From: "Aneesh Kumar K.V" X-Patchwork-Id: 181527 Message-Id: <1346749289-16986-9-git-send-email-aneesh.kumar@linux.vnet.ibm.com> To: benh@kernel.crashing.org, paulus@samba.org Cc: linuxppc-dev@lists.ozlabs.org, "Aneesh Kumar K.V" Date: Tue, 4 Sep 2012 14:31:25 +0530 From: "Aneesh Kumar K.V" slice array size and slice mask size depend on PGTABLE_RANGE. We can't directly include pgtable.h in these header because there is a circular dependency. So add compile time check for these values. Reviewed-by: Paul Mackerras Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/mmu-hash64.h | 13 ++++++++----- arch/powerpc/include/asm/page_64.h | 16 ++++++++++++---- arch/powerpc/include/asm/pgtable-ppc64.h | 8 ++++++++ 3 files changed, 28 insertions(+), 9 deletions(-) diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h index 8f05eec..8c5c5a4 100644 --- a/arch/powerpc/include/asm/mmu-hash64.h +++ b/arch/powerpc/include/asm/mmu-hash64.h @@ -420,6 +420,13 @@ extern void slb_set_size(u16 size); srdi rx,rx,VSID_BITS_##size; /* extract 2^VSID_BITS bit */ \ add rt,rt,rx +/* 4 bits per slice and we have one slice per 1TB */ +#if 0 /* We can't directly include pgtable.h hence this hack */ +#define SLICE_ARRAY_SIZE (PGTABLE_RANGE >> 41) +#else +/* Right now we only support 64TB */ +#define SLICE_ARRAY_SIZE 32 +#endif #ifndef __ASSEMBLY__ @@ -464,11 +471,7 @@ typedef struct { #ifdef CONFIG_PPC_MM_SLICES u64 low_slices_psize; /* SLB page size encodings */ - /* - * Right now we support 64TB and 4 bits for each - * 1TB slice we need 32 bytes for 64TB. - */ - unsigned char high_slices_psize[32]; /* 4 bits per slice for now */ + unsigned char high_slices_psize[SLICE_ARRAY_SIZE]; #else u16 sllp; /* SLB page size encoding */ #endif diff --git a/arch/powerpc/include/asm/page_64.h b/arch/powerpc/include/asm/page_64.h index 6c9bef4..b55beb4 100644 --- a/arch/powerpc/include/asm/page_64.h +++ b/arch/powerpc/include/asm/page_64.h @@ -78,14 +78,22 @@ extern u64 ppc64_pft_size; #define GET_LOW_SLICE_INDEX(addr) ((addr) >> SLICE_LOW_SHIFT) #define GET_HIGH_SLICE_INDEX(addr) ((addr) >> SLICE_HIGH_SHIFT) +/* 1 bit per slice and we have one slice per 1TB */ +#if 0 /* We can't directly include pgtable.h hence this hack */ +#define SLICE_MASK_SIZE (PGTABLE_RANGE >> 43) +#else +/* + * Right now we support only 64TB. + * IF we change this we will have to change the type + * of high_slices + */ +#define SLICE_MASK_SIZE 8 +#endif + #ifndef __ASSEMBLY__ struct slice_mask { u16 low_slices; - /* - * This should be derived out of PGTABLE_RANGE. For the current - * max 64TB, u64 should be ok. - */ u64 high_slices; }; diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h b/arch/powerpc/include/asm/pgtable-ppc64.h index 8af1cf2..dea953f 100644 --- a/arch/powerpc/include/asm/pgtable-ppc64.h +++ b/arch/powerpc/include/asm/pgtable-ppc64.h @@ -32,6 +32,14 @@ #endif #endif +#if (PGTABLE_RANGE >> 41) > SLICE_ARRAY_SIZE +#error PGTABLE_RANGE exceeds SLICE_ARRAY_SIZE +#endif + +#if (PGTABLE_RANGE >> 43) > SLICE_MASK_SIZE +#error PGTABLE_RANGE exceeds slice_mask high_slices size +#endif + /* * Define the address range of the kernel non-linear virtual area */