From patchwork Tue Aug 28 11:52:09 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeong-Hyeon Kim X-Patchwork-Id: 180521 X-Patchwork-Delegate: promsoft@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id F30262C0116 for ; Wed, 29 Aug 2012 02:30:59 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3D8FE2808B; Tue, 28 Aug 2012 18:30:25 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id yBITb-TB-GiS; Tue, 28 Aug 2012 18:30:25 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1B57B2808F; Tue, 28 Aug 2012 18:30:09 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 285B228080 for ; Tue, 28 Aug 2012 13:52:14 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id jAQdARhEjlnE for ; Tue, 28 Aug 2012 13:52:13 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pz0-f44.google.com (mail-pz0-f44.google.com [209.85.210.44]) by theia.denx.de (Postfix) with ESMTPS id 78E302807E for ; Tue, 28 Aug 2012 13:52:11 +0200 (CEST) Received: by mail-pz0-f44.google.com with SMTP id f8so3168187dad.3 for ; Tue, 28 Aug 2012 04:52:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=xnPfThHmnG7eIAzwSyBoME3480IfYKmlAnDkz1+SEIw=; b=CFNv2HEtWXPfQ+cSxKxDFP7uTRXakbHkT2d63gqlISEWaRcrN2vPlBCtwcbAhgpS3m 56eO/dWRsTL1+EUgzJHbhyweh5+OwjpF27V20ewC/b8168WQUKhMM6IQ6fOCbfjHvwsf A4Atf36RoE/9BkCudejSYQcQTWzVX8YODCEly/XieE1DAjyG148PHmxMMFpQpD0SmvZg mAp88w83ZFCkcrmmlCAfognwQNMP7W3FP5mIHyhNf9XwY3EkFDD/6TY5LFSrfCaMtAS2 gmvYVEajJCNypXXdfYxK1A7o6jdQSgoBwW4kFIk5HCwf8x7PefNq/bUrvkrPi7B2vibi hmCg== Received: by 10.68.213.5 with SMTP id no5mr42809114pbc.24.1346154731463; Tue, 28 Aug 2012 04:52:11 -0700 (PDT) Received: from jhkim-insignal ([114.200.239.210]) by mx.google.com with ESMTPS id pa6sm16886358pbc.47.2012.08.28.04.52.08 (version=SSLv3 cipher=OTHER); Tue, 28 Aug 2012 04:52:10 -0700 (PDT) From: snow.jhkim@gmail.com To: mk7.kang@samsung.com Date: Tue, 28 Aug 2012 20:52:09 +0900 Message-Id: <1346154729-7452-1-git-send-email-jhkim@insignal.co.kr> X-Mailer: git-send-email 1.7.1 X-Mailman-Approved-At: Tue, 28 Aug 2012 18:30:05 +0200 Cc: u-boot@lists.denx.de, Jeong-Hyeon Kim Subject: [U-Boot] [PATCH 2/4] EXYNOS: add XXTI for clock source X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Jeong-Hyeon Kim Exynos SoC series are various and cover the different range of MCLK. Several clock setting is based on MPLL, but it's to easy change depend on board configuration. So, common setting of clock need for cover the various type of memory. System clock (XXTI) is one of solution for it. Signed-off-by: Jeong-Hyeon Kim --- arch/arm/cpu/armv7/exynos/clock.c | 16 ++++++++++++---- 1 files changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 4f3b451..680aeeb 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -246,7 +246,9 @@ static unsigned long exynos4_get_pwm_clk(void) sel = readl(&clk->src_peril0); sel = (sel >> 24) & 0xf; - if (sel == 0x6) + if (sel == 0x0 || sel == 0x1) + sclk = CONFIG_SYS_CLK_FREQ; + else if (sel == 0x6) sclk = get_pll_clk(MPLL); else if (sel == 0x7) sclk = get_pll_clk(EPLL); @@ -314,7 +316,9 @@ static unsigned long exynos4_get_uart_clk(int dev_index) sel = readl(&clk->src_peril0); sel = (sel >> (dev_index << 2)) & 0xf; - if (sel == 0x6) + if (sel == 0x0 || sel == 0x1) + sclk = CONFIG_SYS_CLK_FREQ; + else if (sel == 0x6) sclk = get_pll_clk(MPLL); else if (sel == 0x7) sclk = get_pll_clk(EPLL); @@ -361,7 +365,9 @@ static unsigned long exynos5_get_uart_clk(int dev_index) sel = readl(&clk->src_peric0); sel = (sel >> (dev_index << 2)) & 0xf; - if (sel == 0x6) + if (sel == 0x0 || sel == 0x1) + sclk = CONFIG_SYS_CLK_FREQ; + else if (sel == 0x6) sclk = get_pll_clk(MPLL); else if (sel == 0x7) sclk = get_pll_clk(EPLL); @@ -462,7 +468,9 @@ static unsigned long exynos4_get_lcd_clk(void) * 0x7: SCLK_EPLL * 0x8: SCLK_VPLL */ - if (sel == 0x6) + if (sel == 0x0 || sel == 0x1) + sclk = CONFIG_SYS_CLK_FREQ; + else if (sel == 0x6) sclk = get_pll_clk(MPLL); else if (sel == 0x7) sclk = get_pll_clk(EPLL);