diff mbox

mtd: cfi_cmdset_0001: Fix problem with unlocking timeout

Message ID 1346146453-30196-1-git-send-email-sr@denx.de
State Accepted
Commit 7be1f6b9a1ae3476a424380b52aad7c14c3273ab
Headers show

Commit Message

Stefan Roese Aug. 28, 2012, 9:34 a.m. UTC 
Unlocking may take up to 1.4 seconds on some Intel flashes. So
lets use a max. of 1.5 seconds (1500ms) as timeout.

See "Clear Block Lock-Bits Time" on page 40 in
"3 Volt Intel StrataFlash Memory" 28F128J3,28F640J3,28F320J3 manual
from February 2003

This patch also fixes some other problems with this timeout:

- Don't use HZ in timeout "calculation"!
  While testing we noticed that an unlocking timeout occured with
  HZ=1000 and didn't occur with HZ=300. This was because the
  timeout parameter was calculated differently depending on the
  HZ value. Now a fixed value of 1500ms is used.

- The last parameter of WAIT_TIMEOUT (defined to
  inval_cache_and_wait_for_operation) has to be passed in
  micro-seconds. So multiply the ms value with 1000 and not 100
  to calculate this value.

- Use variable name "mdelay" instead of misleading "udelay".

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stephan Gatzka <stephan.gatzka@hbm.com>
Cc: Andreas Friesen <andreas.friesen@hbm.com>
---
 drivers/mtd/chips/cfi_cmdset_0001.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

Comments

Stephan Gatzka Aug. 28, 2012, 5:51 p.m. UTC | #1 
> Signed-off-by: Stefan Roese <sr@denx.de>
 > Cc: Stephan Gatzka <stephan.gatzka@hbm.com>
 > Cc: Andreas Friesen <andreas.friesen@hbm.com>

Successfully tested on MPC5200b with Intel StrataFlash using different 
values for HZ.

No problems, so

Tested-by: Stephan Gatzka <stephan@gatzka.org>
Artem Bityutskiy Aug. 30, 2012, 7:02 a.m. UTC | #2 
On Tue, 2012-08-28 at 11:34 +0200, Stefan Roese wrote:
> Unlocking may take up to 1.4 seconds on some Intel flashes. So
> lets use a max. of 1.5 seconds (1500ms) as timeout.
> 
> See "Clear Block Lock-Bits Time" on page 40 in
> "3 Volt Intel StrataFlash Memory" 28F128J3,28F640J3,28F320J3 manual
> from February 2003

Pushed to l2-mtd.git, thanks!

Artem.
diff mbox

Patch

diff --git a/drivers/mtd/chips/cfi_cmdset_0001.c b/drivers/mtd/chips/cfi_cmdset_0001.c
index dbbd2ed..7751443 100644
--- a/drivers/mtd/chips/cfi_cmdset_0001.c
+++ b/drivers/mtd/chips/cfi_cmdset_0001.c
@@ -2043,7 +2043,7 @@  static int __xipram do_xxlock_oneblock(struct map_info *map, struct flchip *chip
 {
 	struct cfi_private *cfi = map->fldrv_priv;
 	struct cfi_pri_intelext *extp = cfi->cmdset_priv;
-	int udelay;
+	int mdelay;
 	int ret;
 
 	adr += chip->start;
@@ -2072,9 +2072,17 @@  static int __xipram do_xxlock_oneblock(struct map_info *map, struct flchip *chip
 	 * If Instant Individual Block Locking supported then no need
 	 * to delay.
 	 */
-	udelay = (!extp || !(extp->FeatureSupport & (1 << 5))) ? 1000000/HZ : 0;
+	/*
+	 * Unlocking may take up to 1.4 seconds on some Intel flashes. So
+	 * lets use a max of 1.5 seconds (1500ms) as timeout.
+	 *
+	 * See "Clear Block Lock-Bits Time" on page 40 in
+	 * "3 Volt Intel StrataFlash Memory" 28F128J3,28F640J3,28F320J3 manual
+	 * from February 2003
+	 */
+	mdelay = (!extp || !(extp->FeatureSupport & (1 << 5))) ? 1500 : 0;
 
-	ret = WAIT_TIMEOUT(map, chip, adr, udelay, udelay * 100);
+	ret = WAIT_TIMEOUT(map, chip, adr, mdelay, mdelay * 1000);
 	if (ret) {
 		map_write(map, CMD(0x70), adr);
 		chip->state = FL_STATUS;