From patchwork Tue Aug 28 06:36:13 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jia Liu X-Patchwork-Id: 180359 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id B42E72C008D for ; Tue, 28 Aug 2012 17:37:14 +1000 (EST) Received: from localhost ([::1]:53899 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1T6FRK-0006j4-5n for incoming@patchwork.ozlabs.org; Tue, 28 Aug 2012 02:38:18 -0400 Received: from eggs.gnu.org ([208.118.235.92]:40331) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1T6FQV-0004m1-NR for qemu-devel@nongnu.org; Tue, 28 Aug 2012 02:37:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1T6FQR-0002ql-C3 for qemu-devel@nongnu.org; Tue, 28 Aug 2012 02:37:27 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:39473) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1T6FQR-0002lT-5W for qemu-devel@nongnu.org; Tue, 28 Aug 2012 02:37:23 -0400 Received: by mail-pb0-f45.google.com with SMTP id jt11so8730133pbb.4 for ; Mon, 27 Aug 2012 23:37:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :content-type; bh=Hl2shaDlGNqMvZJhSe94TJ7kthBikQRW8Om3Gmx6tNw=; b=aYtTlS32t/JMM2OQi8+oWbcSBzI+SRXoPQBWEOj7A+yIXZjyRQQ1RpjcaT5VPZLHIM +gtlB1Ie+ZPyB+BbEvWJGEVMRm8QTlwo3D7OGBM8ck41f19E/jQCs8YWphtLbwDPHytF wujXnZDRJx4sjQvQPjAQPcMfAj3OAl5t54Z1V3+MkUxCwxCO7ZYg9ORgXfVNGMEHP6PT PF7ywG5nbvnKtuplKBfq1g6sj24fXa6Vop1rmXUFxa1WDY0TVylUyveEc7d5Wz6Bs18a eSIf6V/QnIwCrwSIdlXj5HZxEGKWvrPLrT4bwIjU1vC6pmLIpZD5qDYfeC+z8HzlxV4Q jF3Q== Received: by 10.68.227.70 with SMTP id ry6mr39952121pbc.53.1346135842738; Mon, 27 Aug 2012 23:37:22 -0700 (PDT) Received: from localhost ([1.202.183.51]) by mx.google.com with ESMTPS id pf10sm16369104pbc.56.2012.08.27.23.37.18 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 27 Aug 2012 23:37:21 -0700 (PDT) From: Jia Liu To: qemu-devel@nongnu.org Date: Tue, 28 Aug 2012 14:36:13 +0800 Message-Id: <1346135785-12119-3-git-send-email-proljc@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1346135785-12119-1-git-send-email-proljc@gmail.com> References: <1346135785-12119-1-git-send-email-proljc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Cc: aurelien@aurel32.net Subject: [Qemu-devel] [PATCH v7 02/14] target-mips-ase-dsp: Add dsp resources access check X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add MIPS ASE DSP resources access check. Signed-off-by: Jia Liu --- linux-user/main.c | 6 ++++++ target-mips/cpu.h | 8 ++++++-- target-mips/helper.c | 3 +++ target-mips/op_helper.c | 19 +++++++++++++++++++ target-mips/translate.c | 23 +++++++++++++++++++++++ 5 files changed, 57 insertions(+), 2 deletions(-) diff --git a/linux-user/main.c b/linux-user/main.c index 7dea084..f70b31d 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -2294,6 +2294,12 @@ done_syscall: queue_signal(env, info.si_signo, &info); } break; + case EXCP_DSPDIS: + info.si_signo = TARGET_SIGILL; + info.si_errno = 0; + info.si_code = TARGET_ILL_ILLOPC; + queue_signal(env, info.si_signo, &info); + break; default: // error: fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", diff --git a/target-mips/cpu.h b/target-mips/cpu.h index ce3467f..0aada15 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -415,7 +415,7 @@ struct CPUMIPSState { int error_code; uint32_t hflags; /* CPU State */ /* TMASK defines different execution modes */ -#define MIPS_HFLAG_TMASK 0x007FF +#define MIPS_HFLAG_TMASK 0xC07FF #define MIPS_HFLAG_MODE 0x00007 /* execution modes */ /* The KSU flags must be the lowest bits in hflags. The flag order must be the same as defined for CP0 Status. This allows to use @@ -453,6 +453,9 @@ struct CPUMIPSState { #define MIPS_HFLAG_BDS32 0x10000 /* branch requires 32-bit delay slot */ #define MIPS_HFLAG_BX 0x20000 /* branch exchanges execution mode */ #define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT) + /* MIPS DSP resources access. */ +#define MIPS_HFLAG_DSP 0x40000 /* Enable access to MIPS DSP resources. */ +#define MIPS_HFLAG_DSPR2 0x80000 /* Enable access to MIPS DSPR2 resources. */ target_ulong btarget; /* Jump / branch target */ target_ulong bcond; /* Branch condition (if needed) */ @@ -610,8 +613,9 @@ enum { EXCP_MDMX, EXCP_C2E, EXCP_CACHE, /* 32 */ + EXCP_DSPDIS, - EXCP_LAST = EXCP_CACHE, + EXCP_LAST = EXCP_DSPDIS, }; /* Dummy exception for conditional stores. */ #define EXCP_SC 0x100 diff --git a/target-mips/helper.c b/target-mips/helper.c index 4208bb2..edbe2b0 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -592,6 +592,9 @@ void do_interrupt (CPUMIPSState *env) case EXCP_THREAD: cause = 25; goto set_EPC; + case EXCP_DSPDIS: + cause = 26; + goto set_EPC; case EXCP_CACHE: cause = 30; if (env->CP0_Status & (1 << CP0St_BEV)) { diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index e5bc93e..f2bef2a 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -62,6 +62,25 @@ static inline void compute_hflags(CPUMIPSState *env) if (env->CP0_Status & (1 << CP0St_FR)) { env->hflags |= MIPS_HFLAG_F64; } + if (env->insn_flags & ASE_DSP) { + /* Enables access MIPS DSP resources + on processors implementing one of these ASEs. If the MIPS DSP ASE is + not implemented, this bit must be ignored on write and read as + zero. */ + if (env->CP0_Status & (1 << CP0St_MX)) { + env->hflags |= MIPS_HFLAG_DSP; + } + + } else if (env->insn_flags & ASE_DSPR2) { + /* Enables access MIPS DSP resources + on processors implementing one of these ASEs. If the MIPS DSP ASE is + not implemented, this bit must be ignored on write and read as + zero. */ + if (env->CP0_Status & (1 << CP0St_MX)) { + env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2; + } + + } if (env->insn_flags & ISA_MIPS32R2) { if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { env->hflags |= MIPS_HFLAG_COP1X; diff --git a/target-mips/translate.c b/target-mips/translate.c index b293419..6000183 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -824,6 +824,24 @@ static inline void check_cp1_registers(DisasContext *ctx, int regs) generate_exception(ctx, EXCP_RI); } +/* Verify that the processor is running with DSP instructions enabled. + This is enabled by CP0 Status register MX(24) bit. + */ + +static inline void check_dsp(DisasContext *ctx) +{ + if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP))) { + generate_exception(ctx, EXCP_DSPDIS); + } +} + +static inline void check_dspr2(DisasContext *ctx) +{ + if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSPR2))) { + generate_exception(ctx, EXCP_DSPDIS); + } +} + /* This code generates a "reserved instruction" exception if the CPU does not support the instruction set corresponding to flags. */ static inline void check_insn(CPUMIPSState *env, DisasContext *ctx, int flags) @@ -12861,6 +12879,11 @@ void cpu_state_reset(CPUMIPSState *env) env->hflags |= MIPS_HFLAG_64; } #endif + if (env->cpu_model->insn_flags & ASE_DSPR2) { + env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2; + } else if (env->cpu_model->insn_flags & ASE_DSP) { + env->hflags |= MIPS_HFLAG_DSP; + } env->exception_index = EXCP_NONE; }