From patchwork Mon Aug 27 17:45:54 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Walter Lee X-Patchwork-Id: 180254 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id C264A2C008E for ; Tue, 28 Aug 2012 03:46:21 +1000 (EST) Comment: DKIM? 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(insn_cmpexch, insn_exch, insn_fetchadd, insn_fetchaddgez, insn_fetchand, insn_fetchor): Set type to X1_remote. Index: gcc/config/tilegx/tilegx.md =================================================================== --- gcc/config/tilegx/tilegx.md (revision 190711) +++ gcc/config/tilegx/tilegx.md (working copy) @@ -250,7 +250,7 @@ ;; Define an insn type attribute. This defines what pipes things can go in. (define_attr "type" - "X0,X0_2cycle,X1,X1_branch,X1_2cycle,X1_L2,X1_miss,X01,Y0,Y0_2cycle,Y1,Y2,Y2_2cycle,Y2_L2,Y2_miss,Y01,cannot_bundle,cannot_bundle_3cycle,cannot_bundle_4cycle,nothing" + "X0,X0_2cycle,X1,X1_branch,X1_2cycle,X1_L2,X1_remote,X1_miss,X01,Y0,Y0_2cycle,Y1,Y2,Y2_2cycle,Y2_L2,Y2_miss,Y01,cannot_bundle,cannot_bundle_3cycle,cannot_bundle_4cycle,nothing" (const_string "Y01")) (define_attr "length" "" @@ -2679,7 +2679,7 @@ UNSPEC_INSN_CMPEXCH))] "" "cmpexch\t%0, %r1, %r2" - [(set_attr "type" "X1_L2")]) + [(set_attr "type" "X1_remote")]) (define_insn "insn_cmul" [(set (match_operand:DI 0 "register_operand" "=r") @@ -2817,7 +2817,7 @@ UNSPEC_INSN_EXCH))] "" "exch\t%0, %r1, %r2" - [(set_attr "type" "X1_2cycle")]) + [(set_attr "type" "X1_remote")]) (define_insn "insn_fdouble_add_flags" [(set (match_operand:DI 0 "register_operand" "=r") @@ -2903,7 +2903,7 @@ (match_operand:I48MODE 2 "reg_or_0_operand" "rO")))] "" "fetchadd\t%0, %r1, %r2" - [(set_attr "type" "X1_2cycle")]) + [(set_attr "type" "X1_remote")]) (define_insn "insn_fetchaddgez" [(set (match_operand:I48MODE 0 "register_operand" "=r") @@ -2916,7 +2916,7 @@ UNSPEC_INSN_FETCHADDGEZ))] "" "fetchaddgez\t%0, %r1, %r2" - [(set_attr "type" "X1_2cycle")]) + [(set_attr "type" "X1_remote")]) (define_insn "insn_fetchand" [(set (match_operand:I48MODE 0 "register_operand" "=r") @@ -2928,7 +2928,7 @@ (match_operand:I48MODE 2 "reg_or_0_operand" "rO")))] "" "fetchand\t%0, %r1, %r2" - [(set_attr "type" "X1_2cycle")]) + [(set_attr "type" "X1_remote")]) (define_insn "insn_fetchor" [(set (match_operand:I48MODE 0 "register_operand" "=r") @@ -2940,7 +2940,7 @@ (match_operand:I48MODE 2 "reg_or_0_operand" "rO")))] "" "fetchor\t%0, %r1, %r2" - [(set_attr "type" "X1_2cycle")]) + [(set_attr "type" "X1_remote")]) (define_insn "insn_finv" [(unspec_volatile:VOID [(match_operand 0 "pointer_operand" "rO")] Index: gcc/config/tilegx/tilegx-generic.md =================================================================== --- gcc/config/tilegx/tilegx-generic.md (revision 190711) +++ gcc/config/tilegx/tilegx-generic.md (working copy) @@ -51,6 +51,10 @@ (eq_attr "type" "X1_L2") "X1") +(define_insn_reservation "X1_remote" 50 + (eq_attr "type" "X1_remote") + "X1") + (define_insn_reservation "X1_miss" 80 (eq_attr "type" "X1_miss") "X1") Index: gcc/config/tilegx/sync.md =================================================================== --- gcc/config/tilegx/sync.md (revision 190711) +++ gcc/config/tilegx/sync.md (working copy) @@ -72,7 +72,7 @@ UNSPEC_CMPXCHG))] "" "cmpexch\t%0, %1, %r2" - [(set_attr "type" "X1_L2")]) + [(set_attr "type" "X1_remote")]) (define_expand "atomic_exchange" @@ -101,7 +101,7 @@ UNSPEC_XCHG))] "" "exch\t%0, %1, %r2" - [(set_attr "type" "X1_2cycle")]) + [(set_attr "type" "X1_remote")]) (define_expand "atomic_fetch_" @@ -137,7 +137,7 @@ UNSPEC_ATOMIC))] "" "fetch\t%0, %1, %r2" - [(set_attr "type" "X1_2cycle")]) + [(set_attr "type" "X1_remote")]) (define_expand "atomic_fetch_sub"