From patchwork Fri Aug 24 01:48:51 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Scott Wood X-Patchwork-Id: 179760 X-Patchwork-Delegate: afleming@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 9907A2C0085 for ; Fri, 24 Aug 2012 11:49:23 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2DF1728084; Fri, 24 Aug 2012 03:49:15 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id fAQ1Wr4ocj+s; Fri, 24 Aug 2012 03:49:14 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4811628099; Fri, 24 Aug 2012 03:49:12 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6272E28085 for ; Fri, 24 Aug 2012 03:49:05 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id dLLdOxuRtL4q for ; Fri, 24 Aug 2012 03:49:03 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from tx2outboundpool.messaging.microsoft.com (tx2ehsobe002.messaging.microsoft.com [65.55.88.12]) by theia.denx.de (Postfix) with ESMTPS id 3521B2807D for ; Fri, 24 Aug 2012 03:49:01 +0200 (CEST) Received: from mail85-tx2-R.bigfish.com (10.9.14.242) by TX2EHSOBE012.bigfish.com (10.9.40.32) with Microsoft SMTP Server id 14.1.225.23; Fri, 24 Aug 2012 01:49:00 +0000 Received: from mail85-tx2 (localhost [127.0.0.1]) by mail85-tx2-R.bigfish.com (Postfix) with ESMTP id 74D3C16010A; Fri, 24 Aug 2012 01:49:00 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: -6 X-BigFish: VS-6(zz41c5Nzz1202hzz8275bhz2dh2a8h668h839hd24he5bhf0ah107ah) Received: from mail85-tx2 (localhost.localdomain [127.0.0.1]) by mail85-tx2 (MessageSwitch) id 1345772938893597_2935; Fri, 24 Aug 2012 01:48:58 +0000 (UTC) Received: from TX2EHSMHS034.bigfish.com (unknown [10.9.14.239]) by mail85-tx2.bigfish.com (Postfix) with ESMTP id CD44760052; Fri, 24 Aug 2012 01:48:58 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by TX2EHSMHS034.bigfish.com (10.9.99.134) with Microsoft SMTP Server (TLS) id 14.1.225.23; Fri, 24 Aug 2012 01:48:55 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-005.039d.mgd.msft.net (10.84.1.17) with Microsoft SMTP Server (TLS) id 14.2.309.3; Thu, 23 Aug 2012 20:48:54 -0500 Received: from snotra.am.freescale.net ([10.214.82.253]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id q7O1mpjV021886; Thu, 23 Aug 2012 18:48:54 -0700 From: Scott Wood To: Andy Fleming Date: Thu, 23 Aug 2012 20:48:51 -0500 Message-ID: <1345772931-26567-2-git-send-email-scottwood@freescale.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1345772931-26567-1-git-send-email-scottwood@freescale.com> References: <1345772931-26567-1-git-send-email-scottwood@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 2/2] nand_spl: p1010rdb: optimize ddr init for size X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Data is more compact than code for initializing a bunch of registers. Some of the register intialization is reordered in order to reduce the number of separate register lists to process, but since they were all raw accesses we should not have been relying on the ordering anyway. This saves about 300 bytes. Signed-off-by: Scott Wood --- nand_spl/board/freescale/p1010rdb/nand_boot.c | 110 +++++++++++++++++++------ 1 file changed, 84 insertions(+), 26 deletions(-) diff --git a/nand_spl/board/freescale/p1010rdb/nand_boot.c b/nand_spl/board/freescale/p1010rdb/nand_boot.c index 444d2f2..f1e9df4 100644 --- a/nand_spl/board/freescale/p1010rdb/nand_boot.c +++ b/nand_spl/board/freescale/p1010rdb/nand_boot.c @@ -31,48 +31,106 @@ DECLARE_GLOBAL_DATA_PTR; +static const u32 ddr_regvals_common[] = { + CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE, + CONFIG_SYS_DDR_CS0_BNDS, + CONFIG_SYS_DDR_CS0_CONFIG, + CONFIG_SYS_DDR_CONTROL_2, + CONFIG_SYS_DDR_DATA_INIT, + CONFIG_SYS_DDR_TIMING_4, + CONFIG_SYS_DDR_TIMING_5, + CONFIG_SYS_DDR_ZQ_CONTROL, +}; + +static const u16 ddr_regoffs_common[] = { + offsetof(ccsr_ddr_t, sdram_cfg), + offsetof(ccsr_ddr_t, cs0_bnds), + offsetof(ccsr_ddr_t, cs0_config), + offsetof(ccsr_ddr_t, sdram_cfg_2), + offsetof(ccsr_ddr_t, sdram_data_init), + offsetof(ccsr_ddr_t, timing_cfg_4), + offsetof(ccsr_ddr_t, timing_cfg_5), + offsetof(ccsr_ddr_t, ddr_zq_cntl), +}; + +static const u32 ddr_regvals_slow[] = { + CONFIG_SYS_DDR_TIMING_3_667, + CONFIG_SYS_DDR_TIMING_0_667, + CONFIG_SYS_DDR_TIMING_1_667, + CONFIG_SYS_DDR_TIMING_2_667, + CONFIG_SYS_DDR_MODE_1_667, + CONFIG_SYS_DDR_MODE_2_667, + CONFIG_SYS_DDR_INTERVAL_667, + CONFIG_SYS_DDR_CLK_CTRL_667, + CONFIG_SYS_DDR_WRLVL_CONTROL_667, +}; + +static const u32 ddr_regvals_fast[] = { + CONFIG_SYS_DDR_TIMING_3_800, + CONFIG_SYS_DDR_TIMING_0_800, + CONFIG_SYS_DDR_TIMING_1_800, + CONFIG_SYS_DDR_TIMING_2_800, + CONFIG_SYS_DDR_MODE_1_800, + CONFIG_SYS_DDR_MODE_2_800, + CONFIG_SYS_DDR_INTERVAL_800, + CONFIG_SYS_DDR_CLK_CTRL_800, + CONFIG_SYS_DDR_WRLVL_CONTROL_800, +}; + +static const u16 ddr_regoffs_freq[] = { + offsetof(ccsr_ddr_t, timing_cfg_3), + offsetof(ccsr_ddr_t, timing_cfg_0), + offsetof(ccsr_ddr_t, timing_cfg_1), + offsetof(ccsr_ddr_t, timing_cfg_2), + offsetof(ccsr_ddr_t, sdram_mode), + offsetof(ccsr_ddr_t, sdram_mode_2), + offsetof(ccsr_ddr_t, sdram_interval), + offsetof(ccsr_ddr_t, sdram_clk_cntl), + offsetof(ccsr_ddr_t, ddr_wrlvl_cntl), +}; + +void set_ddr_regs(const u32 *vals, const u16 *offs, int num) +{ + ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; + int i; + + for (i = 0; i < num; i++) { + u32 val = *vals++; + u32 *ptr = (u32 *)(((uintptr_t)ddr) + *offs++); + __raw_writel(val, ptr); + } +} + void sdram_init(u32 ddr_freq_mhz) { + const u32 *regvals; ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; /* mask off E bit */ u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR)); + set_ddr_regs(ddr_regvals_common, ddr_regoffs_common, + ARRAY_SIZE(ddr_regoffs_common)); + __raw_writel(CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE, &ddr->sdram_cfg); __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2); __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); - if (ddr_freq_mhz < 700) { - __raw_writel(CONFIG_SYS_DDR_TIMING_3_667, &ddr->timing_cfg_3); - __raw_writel(CONFIG_SYS_DDR_TIMING_0_667, &ddr->timing_cfg_0); - __raw_writel(CONFIG_SYS_DDR_TIMING_1_667, &ddr->timing_cfg_1); - __raw_writel(CONFIG_SYS_DDR_TIMING_2_667, &ddr->timing_cfg_2); - __raw_writel(CONFIG_SYS_DDR_MODE_1_667, &ddr->sdram_mode); - __raw_writel(CONFIG_SYS_DDR_MODE_2_667, &ddr->sdram_mode_2); - __raw_writel(CONFIG_SYS_DDR_INTERVAL_667, &ddr->sdram_interval); - __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_667, &ddr->sdram_clk_cntl); - __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_667, &ddr->ddr_wrlvl_cntl); - } else { - __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3); - __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0); - __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1); - __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2); - __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode); - __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2); - __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval); - __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl); - __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl); - } + if (ddr_freq_mhz < 700) + regvals = ddr_regvals_slow; + else + regvals = ddr_regvals_fast; - __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); - __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5); - __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); + set_ddr_regs(regvals, ddr_regoffs_freq, ARRAY_SIZE(ddr_regoffs_freq)); /* P1014 and it's derivatives support max 16bit DDR width */ if (svr == SVR_P1014) { - __raw_writel(ddr->sdram_cfg & ~SDRAM_CFG_DBW_MASK, &ddr->sdram_cfg); - __raw_writel(ddr->sdram_cfg | SDRAM_CFG_16_BE, &ddr->sdram_cfg); + u32 val = __raw_readl(&ddr->sdram_cfg); + val &= ~SDRAM_CFG_DBW_MASK; + val |= SDRAM_CFG_16_BE; + __raw_writel(val, &ddr->sdram_cfg); + /* For CS0_BNDS we divide the start and end address by 2, so we can just * shift the entire register to achieve the desired result and the mask * the value so we don't write reserved fields */