[U-Boot,2/2] nand_spl: p1010rdb: optimize ddr init for size

Submitted by Scott Wood on Aug. 24, 2012, 1:48 a.m.

Details

Message ID 1345772931-26567-2-git-send-email-scottwood@freescale.com
State Accepted
Delegated to: Andy Fleming
Headers show

Commit Message

Scott Wood Aug. 24, 2012, 1:48 a.m.
Data is more compact than code for initializing a bunch of registers.

Some of the register intialization is reordered in order to reduce the
number of separate register lists to process, but since they were all raw
accesses we should not have been relying on the ordering anyway.  This saves
about 300 bytes.

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
 nand_spl/board/freescale/p1010rdb/nand_boot.c |  110 +++++++++++++++++++------
 1 file changed, 84 insertions(+), 26 deletions(-)

Patch hide | download patch | download mbox

diff --git a/nand_spl/board/freescale/p1010rdb/nand_boot.c b/nand_spl/board/freescale/p1010rdb/nand_boot.c
index 444d2f2..f1e9df4 100644
--- a/nand_spl/board/freescale/p1010rdb/nand_boot.c
+++ b/nand_spl/board/freescale/p1010rdb/nand_boot.c
@@ -31,48 +31,106 @@ 
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static const u32 ddr_regvals_common[] = {
+	CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE,
+	CONFIG_SYS_DDR_CS0_BNDS,
+	CONFIG_SYS_DDR_CS0_CONFIG,
+	CONFIG_SYS_DDR_CONTROL_2,
+	CONFIG_SYS_DDR_DATA_INIT,
+	CONFIG_SYS_DDR_TIMING_4,
+	CONFIG_SYS_DDR_TIMING_5,
+	CONFIG_SYS_DDR_ZQ_CONTROL,
+};
+
+static const u16 ddr_regoffs_common[] = {
+	offsetof(ccsr_ddr_t, sdram_cfg),
+	offsetof(ccsr_ddr_t, cs0_bnds),
+	offsetof(ccsr_ddr_t, cs0_config),
+	offsetof(ccsr_ddr_t, sdram_cfg_2),
+	offsetof(ccsr_ddr_t, sdram_data_init),
+	offsetof(ccsr_ddr_t, timing_cfg_4),
+	offsetof(ccsr_ddr_t, timing_cfg_5),
+	offsetof(ccsr_ddr_t, ddr_zq_cntl),
+};
+
+static const u32 ddr_regvals_slow[] = {
+	CONFIG_SYS_DDR_TIMING_3_667,
+	CONFIG_SYS_DDR_TIMING_0_667,
+	CONFIG_SYS_DDR_TIMING_1_667,
+	CONFIG_SYS_DDR_TIMING_2_667,
+	CONFIG_SYS_DDR_MODE_1_667,
+	CONFIG_SYS_DDR_MODE_2_667,
+	CONFIG_SYS_DDR_INTERVAL_667,
+	CONFIG_SYS_DDR_CLK_CTRL_667,
+	CONFIG_SYS_DDR_WRLVL_CONTROL_667,
+};
+
+static const u32 ddr_regvals_fast[] = {
+	CONFIG_SYS_DDR_TIMING_3_800,
+	CONFIG_SYS_DDR_TIMING_0_800,
+	CONFIG_SYS_DDR_TIMING_1_800,
+	CONFIG_SYS_DDR_TIMING_2_800,
+	CONFIG_SYS_DDR_MODE_1_800,
+	CONFIG_SYS_DDR_MODE_2_800,
+	CONFIG_SYS_DDR_INTERVAL_800,
+	CONFIG_SYS_DDR_CLK_CTRL_800,
+	CONFIG_SYS_DDR_WRLVL_CONTROL_800,
+};
+
+static const u16 ddr_regoffs_freq[] = {
+	offsetof(ccsr_ddr_t, timing_cfg_3),
+	offsetof(ccsr_ddr_t, timing_cfg_0),
+	offsetof(ccsr_ddr_t, timing_cfg_1),
+	offsetof(ccsr_ddr_t, timing_cfg_2),
+	offsetof(ccsr_ddr_t, sdram_mode),
+	offsetof(ccsr_ddr_t, sdram_mode_2),
+	offsetof(ccsr_ddr_t, sdram_interval),
+	offsetof(ccsr_ddr_t, sdram_clk_cntl),
+	offsetof(ccsr_ddr_t, ddr_wrlvl_cntl),
+};
+
+void set_ddr_regs(const u32 *vals, const u16 *offs, int num)
+{
+	ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+	int i;
+
+	for (i = 0; i < num; i++) {
+		u32 val = *vals++;
+		u32 *ptr = (u32 *)(((uintptr_t)ddr) + *offs++);
+		__raw_writel(val, ptr);
+	}
+}
+
 void sdram_init(u32 ddr_freq_mhz)
 {
+	const u32 *regvals;
 	ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
 	/* mask off E bit */
 	u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR));
 
+	set_ddr_regs(ddr_regvals_common, ddr_regoffs_common,
+		ARRAY_SIZE(ddr_regoffs_common));
+
 	__raw_writel(CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE, &ddr->sdram_cfg);
 	__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
 	__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
 	__raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
 	__raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
 
-	if (ddr_freq_mhz < 700) {
-		__raw_writel(CONFIG_SYS_DDR_TIMING_3_667, &ddr->timing_cfg_3);
-		__raw_writel(CONFIG_SYS_DDR_TIMING_0_667, &ddr->timing_cfg_0);
-		__raw_writel(CONFIG_SYS_DDR_TIMING_1_667, &ddr->timing_cfg_1);
-		__raw_writel(CONFIG_SYS_DDR_TIMING_2_667, &ddr->timing_cfg_2);
-		__raw_writel(CONFIG_SYS_DDR_MODE_1_667, &ddr->sdram_mode);
-		__raw_writel(CONFIG_SYS_DDR_MODE_2_667, &ddr->sdram_mode_2);
-		__raw_writel(CONFIG_SYS_DDR_INTERVAL_667, &ddr->sdram_interval);
-		__raw_writel(CONFIG_SYS_DDR_CLK_CTRL_667, &ddr->sdram_clk_cntl);
-		__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_667, &ddr->ddr_wrlvl_cntl);
-	} else {
-		__raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
-		__raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
-		__raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
-		__raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
-		__raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode);
-		__raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2);
-		__raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval);
-		__raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl);
-		__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl);
-	}
+	if (ddr_freq_mhz < 700)
+		regvals = ddr_regvals_slow;
+	else
+		regvals = ddr_regvals_fast;
 
-	__raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
-	__raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
+	set_ddr_regs(regvals, ddr_regoffs_freq, ARRAY_SIZE(ddr_regoffs_freq));
 
 	/* P1014 and it's derivatives support max 16bit DDR width */
 	if (svr == SVR_P1014) {
-		__raw_writel(ddr->sdram_cfg & ~SDRAM_CFG_DBW_MASK, &ddr->sdram_cfg);
-		__raw_writel(ddr->sdram_cfg | SDRAM_CFG_16_BE, &ddr->sdram_cfg);
+		u32 val = __raw_readl(&ddr->sdram_cfg);
+		val &= ~SDRAM_CFG_DBW_MASK;
+		val |= SDRAM_CFG_16_BE;
+		__raw_writel(val, &ddr->sdram_cfg);
+
 		/* For CS0_BNDS we divide the start and end address by 2, so we can just
 		 * shift the entire register to achieve the desired result and the mask
 		 * the value so we don't write reserved fields */