diff mbox

[SH] PR 39423 - Add support for SH2A movu.w insn

Message ID 1345540417.2156.13.camel@yam-132-YW-E178-FTW
State New
Headers show

Commit Message

Oleg Endo Aug. 21, 2012, 9:13 a.m. UTC 
Hello,

This adds support for SH2A's movu.w insn for memory addressing cases as
described in the PR.
Tested on rev 190546 with
make -k check RUNTESTFLAGS="--target_board=sh-sim
\{-m2/-ml,-m2/-mb,-m2a/-mb,-m4/-ml,-m4/-mb,-m4a/-ml,-m4a/-mb}"

and no new failures.
OK?

Cheers,
Oleg

ChangeLog:

	PR target/39423
	* config/sh/sh.md (*movhi_index_disp): Add support for SH2A 
	movu.w insn.

testsuite/ChangeLog:

	PR target/39423
	* gcc.target/sh/pr39423-2.c: New.

Comments

Kaz Kojima Aug. 21, 2012, 10:40 p.m. UTC | #1 
Oleg Endo <oleg.endo@t-online.de> wrote:
> This adds support for SH2A's movu.w insn for memory addressing cases as
> described in the PR.
> Tested on rev 190546 with
> make -k check RUNTESTFLAGS="--target_board=sh-sim
> \{-m2/-ml,-m2/-mb,-m2a/-mb,-m4/-ml,-m4/-mb,-m4a/-ml,-m4a/-mb}"
> 
> and no new failures.
> OK?

OK.

Regards,
	kaz
diff mbox

Patch

Index: gcc/config/sh/sh.md
===================================================================
--- gcc/config/sh/sh.md	(revision 190459)
+++ gcc/config/sh/sh.md	(working copy)
@@ -5667,12 +5667,35 @@ 
    (clobber (reg:SI T_REG))]
   "TARGET_SH1"
   "#"
-  "&& 1"
-  [(parallel [(set (match_dup 0) (sign_extend:SI (match_dup 1)))
-	      (clobber (reg:SI T_REG))])
-   (set (match_dup 0) (zero_extend:SI (match_dup 2)))]
+  "&& can_create_pseudo_p ()"
+  [(const_int 0)]
 {
-  operands[2] = gen_lowpart (HImode, operands[0]);
+  rtx mem = operands[1];
+  rtx plus0_rtx = XEXP (mem, 0);
+  rtx plus1_rtx = XEXP (plus0_rtx, 0);
+  rtx mult_rtx = XEXP (plus1_rtx, 0);
+
+  rtx op_1 = XEXP (mult_rtx, 0);
+  rtx op_2 = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1))));
+  rtx op_3 = XEXP (plus1_rtx, 1);
+  rtx op_4 = XEXP (plus0_rtx, 1);
+  rtx op_5 = gen_reg_rtx (SImode);
+  rtx op_6 = gen_reg_rtx (SImode);
+  rtx op_7 = replace_equiv_address (mem, gen_rtx_PLUS (SImode, op_6, op_4));
+
+  emit_insn (gen_ashlsi3 (op_5, op_1, op_2));
+  emit_insn (gen_addsi3 (op_6, op_5, op_3));
+
+  /* On SH2A the movu.w insn can be used for zero extending loads.  */
+  if (TARGET_SH2A)
+    emit_insn (gen_zero_extendhisi2 (operands[0], op_7));
+  else
+    {
+      emit_insn (gen_extendhisi2 (operands[0], op_7));
+      emit_insn (gen_zero_extendhisi2 (operands[0],
+				       gen_lowpart (HImode, operands[0])));
+    }
+  DONE;
 })
 
 (define_insn_and_split "*movsi_index_disp"
Index: gcc/testsuite/gcc.target/sh/pr39423-2.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr39423-2.c	(revision 0)
+++ gcc/testsuite/gcc.target/sh/pr39423-2.c	(revision 0)
@@ -0,0 +1,14 @@ 
+/* Check that displacement addressing is used for indexed addresses with a
+   small offset, instead of re-calculating the index and that the movu.w
+   instruction is used on SH2A.  */
+/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
+/* { dg-final { scan-assembler-not "add\t#1" } } */
+/* { dg-final { scan-assembler "movu.w" } } */
+
+int
+test_00 (unsigned short tab[], int index)
+{
+  return tab[index + 1];
+}