Message ID | 1345531999-17872-5-git-send-email-proljc@gmail.com |
---|---|
State | New |
Headers | show |
On Tue, Aug 21, 2012 at 02:53:10PM +0800, Jia Liu wrote: > Add MIPS ASE DSP Load instructions. > > Signed-off-by: Jia Liu <proljc@gmail.com> > --- > target-mips/translate.c | 69 +++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 69 insertions(+) > > diff --git a/target-mips/translate.c b/target-mips/translate.c > index b049238..f154f09 100644 > --- a/target-mips/translate.c > +++ b/target-mips/translate.c > @@ -313,6 +313,9 @@ enum { > OPC_MODU_G_2E = 0x23 | OPC_SPECIAL3, > OPC_DMOD_G_2E = 0x26 | OPC_SPECIAL3, > OPC_DMODU_G_2E = 0x27 | OPC_SPECIAL3, > + > + /* MIPS DSP Load */ > + OPC_LX_DSP = 0x0A | OPC_SPECIAL3, > }; > > /* BSHFL opcodes */ > @@ -340,6 +343,17 @@ enum { > #endif > }; > > +#define MASK_LX(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) > +/* MIPS DSP Load */ > +enum { > + OPC_LBUX = (0x06 << 6) | OPC_LX_DSP, > + OPC_LHX = (0x04 << 6) | OPC_LX_DSP, > + OPC_LWX = (0x00 << 6) | OPC_LX_DSP, > +#if defined(TARGET_MIPS64) > + OPC_LDX = (0x08 << 6) | OPC_LX_DSP, > +#endif > +}; > + > /* Coprocessor 0 (rs field) */ > #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21)) > > @@ -12124,6 +12138,61 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) > check_insn(env, ctx, INSN_LOONGSON2E); > gen_loongson_integer(ctx, op1, rd, rs, rt); > break; > + case OPC_LX_DSP: > + op2 = MASK_LX(ctx->opcode); > + switch (op2) { > + case OPC_LBUX: > + check_insn(env, ctx, ASE_DSP); How about factorizing the check_insn() code one level above? > + { > + TCGv addr = tcg_temp_new(); > + > + save_cpu_state(ctx, 1); I don't think you need to save pc here, they are normal load instructions. > + gen_op_addr_add(ctx, addr, cpu_gpr[rs], cpu_gpr[rt]); > + op_ld_lbu(cpu_gpr[rd], addr, ctx); > + tcg_temp_free(addr); > + break; > + } > + case OPC_LHX: > + check_insn(env, ctx, ASE_DSP); > + { > + TCGv addr = tcg_temp_new(); > + > + save_cpu_state(ctx, 1); > + gen_op_addr_add(ctx, addr, cpu_gpr[rs], cpu_gpr[rt]); > + op_ld_lh(cpu_gpr[rd], addr, ctx); > + tcg_temp_free(addr); > + break; > + } > + case OPC_LWX: > + check_insn(env, ctx, ASE_DSP); > + { > + TCGv addr = tcg_temp_new(); > + > + save_cpu_state(ctx, 1); > + gen_op_addr_add(ctx, addr, cpu_gpr[rs], cpu_gpr[rt]); > + op_ld_lw(cpu_gpr[rd], addr, ctx); > + tcg_temp_free(addr); > + break; > + } > +#if defined(TARGET_MIPS64) > + case OPC_LDX: > + check_insn(env, ctx, ASE_DSP); > + { > + TCGv addr = tcg_temp_new(); > + > + save_cpu_state(ctx, 1); > + gen_op_addr_add(ctx, addr, cpu_gpr[rs], cpu_gpr[rt]); > + op_ld_ld(cpu_gpr[rd], addr, ctx); > + tcg_temp_free(addr); > + break; > + } > +#endif > + default: /* Invalid */ > + MIPS_INVAL("MASK LX"); > + generate_exception(ctx, EXCP_RI); > + break; > + } > + break; > #if defined(TARGET_MIPS64) > case OPC_DEXTM ... OPC_DEXT: > case OPC_DINSM ... OPC_DINS: > -- > 1.7.9.5 > >
diff --git a/target-mips/translate.c b/target-mips/translate.c index b049238..f154f09 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -313,6 +313,9 @@ enum { OPC_MODU_G_2E = 0x23 | OPC_SPECIAL3, OPC_DMOD_G_2E = 0x26 | OPC_SPECIAL3, OPC_DMODU_G_2E = 0x27 | OPC_SPECIAL3, + + /* MIPS DSP Load */ + OPC_LX_DSP = 0x0A | OPC_SPECIAL3, }; /* BSHFL opcodes */ @@ -340,6 +343,17 @@ enum { #endif }; +#define MASK_LX(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) +/* MIPS DSP Load */ +enum { + OPC_LBUX = (0x06 << 6) | OPC_LX_DSP, + OPC_LHX = (0x04 << 6) | OPC_LX_DSP, + OPC_LWX = (0x00 << 6) | OPC_LX_DSP, +#if defined(TARGET_MIPS64) + OPC_LDX = (0x08 << 6) | OPC_LX_DSP, +#endif +}; + /* Coprocessor 0 (rs field) */ #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21)) @@ -12124,6 +12138,61 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) check_insn(env, ctx, INSN_LOONGSON2E); gen_loongson_integer(ctx, op1, rd, rs, rt); break; + case OPC_LX_DSP: + op2 = MASK_LX(ctx->opcode); + switch (op2) { + case OPC_LBUX: + check_insn(env, ctx, ASE_DSP); + { + TCGv addr = tcg_temp_new(); + + save_cpu_state(ctx, 1); + gen_op_addr_add(ctx, addr, cpu_gpr[rs], cpu_gpr[rt]); + op_ld_lbu(cpu_gpr[rd], addr, ctx); + tcg_temp_free(addr); + break; + } + case OPC_LHX: + check_insn(env, ctx, ASE_DSP); + { + TCGv addr = tcg_temp_new(); + + save_cpu_state(ctx, 1); + gen_op_addr_add(ctx, addr, cpu_gpr[rs], cpu_gpr[rt]); + op_ld_lh(cpu_gpr[rd], addr, ctx); + tcg_temp_free(addr); + break; + } + case OPC_LWX: + check_insn(env, ctx, ASE_DSP); + { + TCGv addr = tcg_temp_new(); + + save_cpu_state(ctx, 1); + gen_op_addr_add(ctx, addr, cpu_gpr[rs], cpu_gpr[rt]); + op_ld_lw(cpu_gpr[rd], addr, ctx); + tcg_temp_free(addr); + break; + } +#if defined(TARGET_MIPS64) + case OPC_LDX: + check_insn(env, ctx, ASE_DSP); + { + TCGv addr = tcg_temp_new(); + + save_cpu_state(ctx, 1); + gen_op_addr_add(ctx, addr, cpu_gpr[rs], cpu_gpr[rt]); + op_ld_ld(cpu_gpr[rd], addr, ctx); + tcg_temp_free(addr); + break; + } +#endif + default: /* Invalid */ + MIPS_INVAL("MASK LX"); + generate_exception(ctx, EXCP_RI); + break; + } + break; #if defined(TARGET_MIPS64) case OPC_DEXTM ... OPC_DEXT: case OPC_DINSM ... OPC_DINS:
Add MIPS ASE DSP Load instructions. Signed-off-by: Jia Liu <proljc@gmail.com> --- target-mips/translate.c | 69 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+)