From patchwork Mon Aug 20 23:41:42 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Meador Inge X-Patchwork-Id: 178942 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 656522C008D for ; Tue, 21 Aug 2012 09:41:58 +1000 (EST) Received: from localhost ([::1]:49319 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1T3bbX-00049l-Gr for incoming@patchwork.ozlabs.org; Mon, 20 Aug 2012 19:41:55 -0400 Received: from eggs.gnu.org ([208.118.235.92]:47077) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1T3bbQ-00049g-Qi for qemu-devel@nongnu.org; Mon, 20 Aug 2012 19:41:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1T3bbP-0001Hy-Ep for qemu-devel@nongnu.org; Mon, 20 Aug 2012 19:41:48 -0400 Received: from relay1.mentorg.com ([192.94.38.131]:47906) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1T3bbP-0001Hs-8d for qemu-devel@nongnu.org; Mon, 20 Aug 2012 19:41:47 -0400 Received: from svr-orw-exc-10.mgc.mentorg.com ([147.34.98.58]) by relay1.mentorg.com with esmtp id 1T3bbM-0001JX-5e from meador_inge@mentor.com ; Mon, 20 Aug 2012 16:41:44 -0700 Received: from SVR-ORW-FEM-03.mgc.mentorg.com ([147.34.97.39]) by SVR-ORW-EXC-10.mgc.mentorg.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 20 Aug 2012 16:41:44 -0700 Received: from dhalsim.mgc.mentorg.com (147.34.91.1) by svr-orw-fem-03.mgc.mentorg.com (147.34.97.39) with Microsoft SMTP Server id 14.1.289.1; Mon, 20 Aug 2012 16:41:43 -0700 From: Meador Inge To: Date: Mon, 20 Aug 2012 18:41:42 -0500 Message-ID: <1345506102-8444-1-git-send-email-meadori@codesourcery.com> X-Mailer: git-send-email 1.7.7.6 MIME-Version: 1.0 X-OriginalArrivalTime: 20 Aug 2012 23:41:44.0047 (UTC) FILETIME=[5AFE17F0:01CD7F2D] X-detected-operating-system: by eggs.gnu.org: Solaris 10 (beta) X-Received-From: 192.94.38.131 Cc: aurelien@aurel32.net Subject: [Qemu-devel] [PATCH] target-mips: Enable access to required RDHWR hardware registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org While running in the usermode emulator all of the MIPS32r2 *required* RDHWR hardware registers should be accessible (the Linux kernel enables access to these same registers). Signed-off-by: Meador Inge --- target-mips/translate.c | 7 +++++-- 1 files changed, 5 insertions(+), 2 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index 47daf85..849e75d 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -12768,8 +12768,11 @@ void cpu_state_reset(CPUMIPSState *env) #if defined(CONFIG_USER_ONLY) env->hflags = MIPS_HFLAG_UM; - /* Enable access to the SYNCI_Step register. */ - env->CP0_HWREna |= (1 << 1); + if (env->insn_flags & ISA_MIPS32R2) { + /* Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR + hardware registers. */ + env->CP0_HWREna |= 0x0000000F; + } if (env->CP0_Config1 & (1 << CP0C1_FP)) { env->hflags |= MIPS_HFLAG_FPU; }