[v2,1/2] ARM: clk-imx35: Fix SSI clock registration

Submitted by Fabio Estevam on Aug. 20, 2012, 12:39 p.m.

Details

Message ID 1345466362-2576-1-git-send-email-fabio.estevam@freescale.com
State New
Headers show

Commit Message

Fabio Estevam Aug. 20, 2012, 12:39 p.m.
SSI block has two types of clock:

ipg: bus clock, the clock needed for accessing registers.
per: peripheral clock, the clock needed for generating the bit rate.

Currently SSI driver only supports slave mode and only need to handle
the ipg clock, because the peripheral clock comes from the master codec.

Only register the ipg clock and do not register the peripheral clock for ssi.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
Changes since v1:
- Use ssi2_gate for imx-ssi.1

 arch/arm/mach-imx/clk-imx35.c |    6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

Comments

Mark Brown Aug. 22, 2012, 7:27 p.m.
On Mon, Aug 20, 2012 at 09:39:22AM -0300, Fabio Estevam wrote:
> SSI block has two types of clock:
> 
> ipg: bus clock, the clock needed for accessing registers.
> per: peripheral clock, the clock needed for generating the bit rate.
> 
> Currently SSI driver only supports slave mode and only need to handle
> the ipg clock, because the peripheral clock comes from the master codec.
> 
> Only register the ipg clock and do not register the peripheral clock for ssi.

Tested-by: Mark Brown <broonie@opensource.wolfsonmicro.com>

in that it stops boot hanging on the board, though it still doesn't make
AC'97 come out of reset happily.  That's probably some separate issue
(pinmux perhaps?) though.
Fabio Estevam Aug. 22, 2012, 7:38 p.m.
On Wed, Aug 22, 2012 at 4:27 PM, Mark Brown
<broonie@opensource.wolfsonmicro.com> wrote:

> Tested-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
>
> in that it stops boot hanging on the board, though it still doesn't make
> AC'97 come out of reset happily.  That's probably some separate issue
> (pinmux perhaps?) though.

Yes, looks like a separate issue.

Did imx_ssi_probe go successfully? What is the error log you are getting?

Regards,

Fabio Estevam
Sascha Hauer Aug. 28, 2012, 7:49 a.m.
On Mon, Aug 20, 2012 at 09:39:22AM -0300, Fabio Estevam wrote:
> SSI block has two types of clock:
> 
> ipg: bus clock, the clock needed for accessing registers.
> per: peripheral clock, the clock needed for generating the bit rate.
> 
> Currently SSI driver only supports slave mode and only need to handle
> the ipg clock, because the peripheral clock comes from the master codec.
> 
> Only register the ipg clock and do not register the peripheral clock for ssi.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

Ok, used this version instead.

Sascha

> ---
> Changes since v1:
> - Use ssi2_gate for imx-ssi.1
> 
>  arch/arm/mach-imx/clk-imx35.c |    6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
> index c6422fb..f7910df 100644
> --- a/arch/arm/mach-imx/clk-imx35.c
> +++ b/arch/arm/mach-imx/clk-imx35.c
> @@ -230,10 +230,8 @@ int __init mx35_clocks_init()
>  	clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
>  	clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1");
>  	clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
> -	clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.0");
> -	clk_register_clkdev(clk[ssi1_div_post], "per", "imx-ssi.0");
> -	clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.1");
> -	clk_register_clkdev(clk[ssi2_div_post], "per", "imx-ssi.1");
> +	clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0");
> +	clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1");
>  	/* i.mx35 has the i.mx21 type uart */
>  	clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0");
>  	clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0");
> -- 
> 1.7.9.5
> 
> 
>
Mark Brown Aug. 28, 2012, 5:13 p.m.
On Wed, Aug 22, 2012 at 04:38:26PM -0300, Fabio Estevam wrote:
> On Wed, Aug 22, 2012 at 4:27 PM, Mark Brown

> > in that it stops boot hanging on the board, though it still doesn't make
> > AC'97 come out of reset happily.  That's probably some separate issue
> > (pinmux perhaps?) though.

> Yes, looks like a separate issue.

> Did imx_ssi_probe go successfully? What is the error log you are getting?

The controller probes but there's no perceptible activity on the pins
when we try to reset the CODEC so no register I/O.
Fabio Estevam Aug. 28, 2012, 5:22 p.m.
On Tue, Aug 28, 2012 at 2:13 PM, Mark Brown
<broonie@opensource.wolfsonmicro.com> wrote:

>> Did imx_ssi_probe go successfully? What is the error log you are getting?
>
> The controller probes but there's no perceptible activity on the pins
> when we try to reset the CODEC so no register I/O.

Take a look at pcm043_ac97_cold_reset/pcm043_ac97_warm_reset at
arch/arm/mach-imx/mach-pcm043.c
to see how GPIO pins are handled for resetting ac97 codec on this platform.

Regards,

Fabio Estevam

Patch hide | download patch | download mbox

diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
index c6422fb..f7910df 100644
--- a/arch/arm/mach-imx/clk-imx35.c
+++ b/arch/arm/mach-imx/clk-imx35.c
@@ -230,10 +230,8 @@  int __init mx35_clocks_init()
 	clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
 	clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1");
 	clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
-	clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.0");
-	clk_register_clkdev(clk[ssi1_div_post], "per", "imx-ssi.0");
-	clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.1");
-	clk_register_clkdev(clk[ssi2_div_post], "per", "imx-ssi.1");
+	clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0");
+	clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1");
 	/* i.mx35 has the i.mx21 type uart */
 	clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0");
 	clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0");