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[wwwdocs] SH 4.8 changes update

Message ID 1345337217.2268.2.camel@yam-132-YW-E178-FTW
State New
Headers show

Commit Message

Oleg Endo Aug. 19, 2012, 12:46 a.m. UTC 
Hello,

This is what has been done so far on the SH side for 4.8.
I hope it's OK.

Cheers,
Oleg

Comments

Kaz Kojima Aug. 19, 2012, 1:35 a.m. UTC | #1 
Oleg Endo <oleg.endo@t-online.de> wrote:
> This is what has been done so far on the SH side for 4.8.
> I hope it's OK.

Looks fine to me.

Regards,
	kaz
Gerald Pfeifer Aug. 19, 2012, 5:20 p.m. UTC | #2 
On Sun, 19 Aug 2012, Oleg Endo wrote:
> This is what has been done so far on the SH side for 4.8.
> I hope it's OK.

Wow, that is quite impressive (and a nice write-up also)!

I see this was already approved, but allow me to suggest some
minor editorial comments...

Index: htdocs/gcc-4.8/changes.html
===================================================================
+    <li>The default alignment settings have been reduced to be less aggresive.

"aggressive"

+      <li>Minor tweaks for code around software atomic sequences that are
+      enabled by <code>-msoft-atomic</code>.</li>

"code for"?  Not sure...

+      <li>A new option <code>-menable-tas</code> will make the compiler
+      generate the <code>tas.b</code> instruction for the
+      <code>__atomic_test_and_set</code> built-in function.</li>

A naive question: Why is this not on by default?  Or is it under
certain circumstances?

+    <li>The <code>fmac</code> instruction will now be emitted by the
+    <code>fmaf</code> standard and built-in function.</li>

"built-in standard function", perhaps?

+    <li>The <code>-mfused-madd</code> option has been depricated in favor of

"deprecated"

+    <li>Added new options <code>-mfsrra</code> and <code>-mfsca</code> to allow
+    the compiler using the <code>fsrra</code> and <code>fsca</code>
+    instructions on CPUs other than SH4A.</li>

How about adding "...SH4A (where they are already on by default)" or
similar?

Gerald
diff mbox

Patch

Index: htdocs/gcc-4.8/changes.html
===================================================================
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-4.8/changes.html,v
retrieving revision 1.10
diff -u -r1.10 changes.html
--- htdocs/gcc-4.8/changes.html	10 Aug 2012 16:25:46 -0000	1.10
+++ htdocs/gcc-4.8/changes.html	19 Aug 2012 00:41:33 -0000
@@ -100,6 +100,70 @@ 
     options to the assembler.</li>
   </ul>
 
+<h3>SH</h3>
+  <ul>
+    <li>The default alignment settings have been reduced to be less aggresive.
+    This results in more compact code for optimization levels other than
+    <code>-Os</code>.</li>
+
+    <li>Improved support for the <code>__atomic</code> built-in functions:
+    <ul>
+      <li>Minor tweaks for code around software atomic sequences that are
+      enabled by <code>-msoft-atomic</code>.</li>
+
+      <li>A new option <code>-menable-tas</code> will make the compiler
+      generate the <code>tas.b</code> instruction for the
+      <code>__atomic_test_and_set</code> built-in function.</li>
+
+      <li>The SH4A instructions <code>movco.l</code> and
+      <code>movli.l</code> are now supported.  They are used to implement some
+      software atomic sequences that are enabled by <code>-msoft-atomic</code>.
+      In addition to that, pure <code>movco.l</code> / <code>movli.l</code>
+      atomic sequences can be enabled with the new option
+      <code>-mhard-atomic</code>.</li>
+    </ul></li>
+
+    <li>Added support for the <code>mov.b</code> and <code>mov.w</code>
+    instructions with displacement addressing.</li>
+
+    <li>Added support for the SH2A instructions <code>movu.b</code> and
+    <code>movu.w</code>.</li>
+
+    <li>Various improvements to code generated for integer arithmetic.</li>
+
+    <li>Improvements to conditional branches and code that involves the T bit.
+    A new option <code>-mzdcbranch</code> tells the compiler to favor
+    zero-displacement branches.  This is enabled by default for SH4 and
+    SH4A.</li>
+
+    <li>The <code>pref</code> instruction will now be emitted by the
+    <code>__builtin_prefetch</code> built-in function for SH3.</li>
+
+    <li>The <code>fmac</code> instruction will now be emitted by the
+    <code>fmaf</code> standard and built-in function.</li>
+
+    <li>The <code>-mfused-madd</code> option has been depricated in favor of
+    the machine-independent <code>-ffp-contract</code> option.  Notice that the
+    <code>fmac</code> instruction will now be generated by default for
+    expressions like <code>a * b + c</code>.  This is due to the compiler
+    default setting <code>-ffp-contract=fast</code>.</li>
+
+    <li>Added new options <code>-mfsrra</code> and <code>-mfsca</code> to allow
+    the compiler using the <code>fsrra</code> and <code>fsca</code>
+    instructions on CPUs other than SH4A.</li>
+
+    <li>Added support for the <code>__builtin_bswap32</code> built-in function.
+    It is now expanded as a sequence of <code>swap.b</code> and
+    <code>swap.w</code> instructions instead of a library function call.</li>
+
+    <li>The behavior of the <code>-mieee</code> option has been fixed and the
+    negative form <code>-mno-ieee</code> has been added to control the IEEE
+    conformance of floating point comparisons.  By default<code>-mieee</code> is
+    now enabled and the option <code>-ffinite-math-only</code> implicitly sets
+    <code>-mno-ieee</code>.</li>
+
+  </ul>
+
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 <h2>Documentation improvements</h2>
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