Patchwork [U-Boot,7/8] powerpc/mpc8xxx DDR: Fall back to raw timing for first controller only

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Submitter York Sun
Date Aug. 17, 2012, 6:22 p.m.
Message ID <1345227763-29584-7-git-send-email-yorksun@freescale.com>
Download mbox | patch
Permalink /patch/178310/
State Awaiting Upstream
Delegated to: Andy Fleming
Headers show

Comments

York Sun - Aug. 17, 2012, 6:22 p.m.
Only the first DIMM of first controller should fall back to raw timing
parameters if SPD is missing or corrupted.

Signed-off-by: York Sun <yorksun@freescale.com>
---
 arch/powerpc/cpu/mpc8xxx/ddr/main.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

Patch

diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
index 4fd4f8f..b47268c 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
@@ -383,7 +383,7 @@  fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 
 				retval = compute_dimm_parameters(spd, pdimm, i);
 #ifdef CONFIG_SYS_DDR_RAW_TIMING
-				if (retval != 0) {
+				if (!i && !j && retval) {
 					printf("SPD error on controller %d! "
 					"Trying fallback to raw timing "
 					"calculation\n", i);