From patchwork Fri Aug 17 15:49:53 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?=C5=81ukasz_Majewski?= X-Patchwork-Id: 178280 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id F23A42C00AA for ; Sat, 18 Aug 2012 01:50:15 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 98E1A28811; Fri, 17 Aug 2012 17:50:14 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id L2Tp9vE+hlWC; Fri, 17 Aug 2012 17:50:14 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 78E5A287F8; Fri, 17 Aug 2012 17:50:12 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 87D27287F8 for ; Fri, 17 Aug 2012 17:50:10 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 6Eb4vvsI13-P for ; Fri, 17 Aug 2012 17:50:08 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mailout3.samsung.com (mailout3.samsung.com [203.254.224.33]) by theia.denx.de (Postfix) with ESMTP id 297AB287F5 for ; Fri, 17 Aug 2012 17:50:06 +0200 (CEST) Received: from epcpsbgm2.samsung.com (mailout3.samsung.com [203.254.224.33]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M8W002LZPBG8R80@mailout3.samsung.com> for u-boot@lists.denx.de; Sat, 18 Aug 2012 00:50:04 +0900 (KST) X-AuditID: cbfee61b-b7faf6d00000476a-48-502e682cb884 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id C1.97.18282.C286E205; Sat, 18 Aug 2012 00:50:04 +0900 (KST) Received: from amdc308.digital.local ([106.116.147.36]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M8W000OLPB6BU20@mmp2.samsung.com> for u-boot@lists.denx.de; Sat, 18 Aug 2012 00:50:04 +0900 (KST) Date: Fri, 17 Aug 2012 17:49:53 +0200 From: Lukasz Majewski To: aneesh@ti.com Message-id: <20120817174953.08add23e@amdc308.digital.local> Organization: SPRC Poland X-Mailer: Claws Mail 3.7.6 (GTK+ 2.20.1; x86_64-pc-linux-gnu) MIME-version: 1.0 Content-type: multipart/mixed; boundary="MP_/7OT0hlOE0TLvqj8kABCHwi2" X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrILMWRmVeSWpSXmKPExsVy+t9jQV2dDL0Ag7UvOS3e7u1kd2D0OHtn B2MAYxSXTUpqTmZZapG+XQJXxpRzT1gK1tlUtHe8ZmpgnGrYxcjJISFgInHhxiwWCFtM4sK9 9WxdjFwcQgLTGSVeXNrPCOEsYJLovPmQDaSKRUBV4uSu/2A2m4CexOe7T5lAbBEBQYmzL1ax gtjMAs4St7ZPBYsLCxhKrLp/gh3E5hWwlvh0ZQPYNn4BSYn2fz+YITbbSsz99YYFokZQ4sfk eywQc1wlNjUvZ53AyDcLSWoWkhSErSXx8NctqLi8xPa3c5hnMXIA2dISy/9xQISlJGb8OcKM qgTEzpa4PHUHI241IGOyJDZsMV3AyL2KUTS1ILmgOCk910ivODG3uDQvXS85P3cTIzginknv YFzVYHGIUYCDUYmH90CZboAQa2JZcWXuIUYJDmYlEd4VH4FCvCmJlVWpRfnxRaU5qcWHGKU5 WJTEeb3+A6UE0hNLUrNTUwtSi2CyTBycUg2Mvaf33b615mHIX5cMQabX71cxWAoZr77u4P84 wunxu1liW8TzgwIFXBx/VM97uPfchVf8jcZLD0cHPNO0uPO9PqTj/a7AdruZJRcLEruXrF+g 5nuvqa1W87RXzYdF8vccQt7/3eJ6ToHJVTOuoU9ks3VXEneyh8zxbe8eT059HZXIMe/NdqHP SizFGYmGWsxFxYkAuYdAmoQCAAA= X-TM-AS-MML: No Cc: u-boot@lists.denx.de, Kyungmin Park Subject: [U-Boot] Performance of the ARM's PL310 L2 cache. X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Hi Aneesh, I've enabled the L2 cache for Trats board. Please find results from performance tests. The test function as well as my way for enabling L2 are attached to this e-mail. I simply left the default configuration (number of ways, associativity) as it is at Linux Kernel's driver. Results: test_l2_cache() performed once: L1 L2 TIME [seconds] OFF OFF 90,359 ON OFF 62,236 ON ON 61,687 L1 speedup: ~33 % L2 speedup (when compared to L1): < 1% test_l2_cache() performed 5000 times: L1 L2 TIME [seconds] OFF OFF 444,9 ON OFF 320,55 ON ON 287,21 L1 speedup: ~28 % L2 speedup (when compared to L1): ~ 10% Normal u-boot operation (from system startup - up till passing execution to kernel). L1 L2 TIME [seconds] OFF OFF 1,813 ON OFF 1,552 ON ON 1,533 As one can observe, for normal u-boot operation there is no significant difference. Have you had similar results with OMAP? Do you do more configuration when enabling the L2 at OMAP? The assembly code presented below (armv7/omap-common/lowlevel_init.S) puzzles me a bit... ENTRY(set_pl310_ctrl_reg) LDR r12, =0x102 @ Set PL310 control register - value in R0 .word 0xe1600070 @ SMC #0 - hand assembled @because -march=armv5 @ call ROM Code API to set control @ register ENDPROC(set_pl310_ctrl_reg) Are there any special operations executed at "ROM Code API"? From ce66526f772e748234d1f4bf3d264df90274e8c3 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Thu, 16 Aug 2012 15:23:49 +0200 Subject: [PATCH] cache: wip: Test program to evaluate if L2 is working. Signed-off-by: Lukasz Majewski --- arch/arm/cpu/armv7/exynos/soc.c | 28 ++++++++++++++++++++++++++++ arch/arm/lib/cache-pl310.c | 2 -- board/samsung/trats/trats.c | 2 ++ include/common.h | 1 + include/configs/trats.h | 3 +++ 5 files changed, 34 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/soc.c b/arch/arm/cpu/armv7/exynos/soc.c index 9e8705f..9660daa 100644 --- a/arch/arm/cpu/armv7/exynos/soc.c +++ b/arch/arm/cpu/armv7/exynos/soc.c @@ -24,6 +24,7 @@ #include #include #include +#include void reset_cpu(ulong addr) { @@ -41,6 +42,7 @@ void enable_caches(void) #ifndef CONFIG_SYS_L2CACHE_OFF void v7_outer_cache_enable(void) { + /* puts("-\n"); */ pl310_enable(); } void v7_outer_cache_disable(void) @@ -48,3 +50,29 @@ void v7_outer_cache_disable(void) pl310_disable(); } #endif + +#define TEST_BUF_SIZE (1024*256) +void test_l2_cache() +{ + int i, j; + u32 *ptr = (u32 *) 0x52000000; + volatile u64 sigma = 0; + + /* Setup the buffer */ + for (i = 0; i < TEST_BUF_SIZE; i++) { + *(ptr + i) = i; + } + + flush_dcache_range((u32) ptr, + (u32) ptr + (TEST_BUF_SIZE * sizeof(u32))); + + /* Here data at Cache is in sync with SDRAM */ + for (j = 0; j < 5000; j++) { + for (i = 0, sigma = 0; i < TEST_BUF_SIZE; i++) + sigma += *(ptr + i); + if (!(j % 500)) + puts("."); + } + + printf("sig: 0x%llx\n", sigma); +} diff --git a/arch/arm/lib/cache-pl310.c b/arch/arm/lib/cache-pl310.c index 76d60cf..885063b 100644 --- a/arch/arm/lib/cache-pl310.c +++ b/arch/arm/lib/cache-pl310.c @@ -120,8 +120,6 @@ void v7_outer_cache_inval_range(u32 start, u32 stop) void pl310_enable(void) { writel(1, &pl310->pl310_ctrl); - printf("p310_ctrl: 0x%x p310_aux_ctrl: 0x%x\n", - readl(&pl310->pl310_ctrl), readl(&pl310->pl310_aux_ctrl)); } void pl310_disable(void) diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index 4f9cb5a..0db22cb 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -72,6 +72,8 @@ int board_init(void) pmic_init(); #endif + test_l2_cache(); + return 0; } diff --git a/include/common.h b/include/common.h index 39859d3..ab4f009 100644 --- a/include/common.h +++ b/include/common.h @@ -570,6 +570,7 @@ int checkdcache (void); void upmconfig (unsigned int, unsigned int *, unsigned int); ulong get_tbclk (void); void reset_cpu (ulong addr); +void test_l2_cache (void); #if defined (CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP) void ft_cpu_setup(void *blob, bd_t *bd); #ifdef CONFIG_PCI diff --git a/include/configs/trats.h b/include/configs/trats.h index 4b2b4d6..f2e5bd9 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -42,6 +42,9 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_SYS_L2CACHE_OFF + #ifndef CONFIG_SYS_L2CACHE_OFF #define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE 0x10502000 -- 1.7.2.3