Patchwork [U-Boot,PATCHv1] ARM: Add Altera SOCFPGA Cyclone5

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Submitter dinguyen@altera.com
Date Aug. 16, 2012, 10:45 p.m.
Message ID <1345157139-19585-1-git-send-email-dinguyen@altera.com>
Download mbox | patch
Permalink /patch/178173/
State Superseded
Delegated to: Marek Vasut
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Comments

dinguyen@altera.com - Aug. 16, 2012, 10:45 p.m.
From: Dinh Nguyen <dinguyen@altera.com>

Add minimal support for Altera's SOCFPGA Cyclone 5 hardware.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Pavel Machek <pavel@denx.de>
---
 MAINTAINERS                                        |    5 +
 Makefile                                           |    2 +-
 arch/arm/cpu/armv7/socfpga/Makefile                |   51 +++++
 arch/arm/cpu/armv7/socfpga/lowlevel_init.S         |   79 +++++++
 arch/arm/cpu/armv7/socfpga/reset_manager.c         |   45 ++++
 arch/arm/cpu/armv7/socfpga/sdram.c                 |   26 +++
 arch/arm/cpu/armv7/socfpga/spl.c                   |  182 +++++++++++++++
 arch/arm/cpu/armv7/socfpga/timer.c                 |  118 ++++++++++
 arch/arm/cpu/armv7/socfpga/u-boot-spl.lds          |   60 +++++
 arch/arm/include/asm/arch-socfpga/reset_manager.h  |   37 +++
 .../include/asm/arch-socfpga/socfpga_base_addrs.h  |   27 +++
 arch/arm/include/asm/arch-socfpga/socfpga_spl.h    |   30 +++
 board/altera/socfpga_cyclone5/Makefile             |   50 ++++
 board/altera/socfpga_cyclone5/socfpga_cyclone5.c   |   97 ++++++++
 boards.cfg                                         |    1 +
 include/configs/socfpga_cyclone5.h                 |  240 ++++++++++++++++++++
 16 files changed, 1049 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/cpu/armv7/socfpga/Makefile
 create mode 100644 arch/arm/cpu/armv7/socfpga/lowlevel_init.S
 create mode 100644 arch/arm/cpu/armv7/socfpga/reset_manager.c
 create mode 100644 arch/arm/cpu/armv7/socfpga/sdram.c
 create mode 100644 arch/arm/cpu/armv7/socfpga/spl.c
 create mode 100644 arch/arm/cpu/armv7/socfpga/timer.c
 create mode 100644 arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
 create mode 100644 arch/arm/include/asm/arch-socfpga/reset_config.h
 create mode 100644 arch/arm/include/asm/arch-socfpga/reset_manager.h
 create mode 100644 arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
 create mode 100644 arch/arm/include/asm/arch-socfpga/socfpga_spl.h
 create mode 100644 board/altera/socfpga_cyclone5/Makefile
 create mode 100644 board/altera/socfpga_cyclone5/socfpga_cyclone5.c
 create mode 100644 include/configs/socfpga_cyclone5.h
Pavel Machek - Aug. 22, 2012, 10:10 p.m.
Hi!

> From: Dinh Nguyen <dinguyen@altera.com>
> 
> Add minimal support for Altera's SOCFPGA Cyclone 5 hardware.

Albert, it seems you should be one merging this...? (Am I right?) Is
there anything we need to fix? Was it too late?

Thanks,
									Pavel
Marek Vasut - Aug. 22, 2012, 10:26 p.m.
Dear dinguyen@altera.com,

> From: Dinh Nguyen <dinguyen@altera.com>
> 
> Add minimal support for Altera's SOCFPGA Cyclone 5 hardware.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> Signed-off-by: Pavel Machek <pavel@denx.de>

[...]

Please CC albert with new arches.

> diff --git a/Makefile b/Makefile
> index 5ce5cc3..12aa372 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -369,7 +369,7 @@ BOARD_SIZE_CHECK =
>  endif
> 
>  # Always append ALL so that arch config.mk's can add custom ones
> -ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map
> +ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)u-boot.img
> $(obj)System.map

This won't slide

>  ALL-$(CONFIG_NAND_U_BOOT) += $(obj)u-boot-nand.bin
>  ALL-$(CONFIG_ONENAND_U_BOOT) += $(obj)u-boot-onenand.bin
[...]

> +/*
> + * Write the reset manager register to cause reset
> + */
> +void reset_cpu(ulong addr)
> +{
> +	/* request a warm reset */
> +	writel(RSTMGR_CTRL_SWWARMRSTREQ_LSB, &reset_manager_base->ctrl);
> +	/* infinite loop here as watchdog will trigger and reset
> +	 * the processor */
> +	while (1)
> +		;
> +}
> +
> +/*
> + * Release peripherals from reset based on handoff
> + */
> +void reset_deassert_peripherals_handoff(void)
> +{
> +	unsigned int val = 0;
> +	writel(val, &reset_manager_base->per_mod_reset);

writel(0, ...

> +}
> diff --git a/arch/arm/cpu/armv7/socfpga/sdram.c
> b/arch/arm/cpu/armv7/socfpga/sdram.c new file mode 100644
> index 0000000..6714983
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/socfpga/sdram.c
> @@ -0,0 +1,26 @@
> +/*
> + *  Copyright (C) 2012 Altera Corporation <www.altera.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <common.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int dram_init(void)
> +{
> +	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
> +	return 0;
> +}

Can all this be concentrated into single file (reset, sdram, etc. all those 
small functions).

> diff --git a/arch/arm/cpu/armv7/socfpga/spl.c
> b/arch/arm/cpu/armv7/socfpga/spl.c new file mode 100644
> index 0000000..7bd1e2f
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/socfpga/spl.c
> @@ -0,0 +1,182 @@
> + /*
> + *  Copyright (C) 2012 Altera Corporation <www.altera.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/u-boot.h>
> +#include <asm/utils.h>
> +#include <asm/arch/socfpga_spl.h>
> +#include <version.h>
> +#include <image.h>
> +#include <malloc.h>
> +#include <asm/arch/reset_manager.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static u32 *boot_params_ptr;
> +static struct spl_image_info spl_image;
> +
> +extern void __malloc_start, __malloc_end, __stack_start;
> +
> +/* Define global data structure pointer to it */
> +static gd_t gdata __attribute__ ((section(".data")));
> +
> +/*
> + * Error action
> + */
> +inline void hang(void)
> +{
> +	puts("### ERROR ### Please RESET the board ###\n");
> +	for (;;)
> +		;
> +}
> +
> +/*
> + * Read the mkimage signature to extract info such as entry point.
> + * The header is generated by tools/mkimage
> + */
> +static unsigned long spl_parse_image_header(const struct image_header
> *header) +{
> +	/* checking for mkimage signature */
> +	if (__be32_to_cpu(header->ih_magic) == IH_MAGIC) {
> +		/* Valid image. Extract information out of header */
> +		spl_image.size = __be32_to_cpu(header->ih_size);
> +		spl_image.entry_point = __be32_to_cpu(header->ih_load);
> +		spl_image.load_addr = __be32_to_cpu(header->ih_load);
> +		spl_image.os = header->ih_os;
> +		spl_image.name = (const char *)&header->ih_name;
> +		spl_image.crc = __be32_to_cpu(header->ih_dcrc);
> +		debug("Subsequent boot image info\n");
> +		debug("   Image Name:   %.*s\n", IH_NMLEN, spl_image.name);
> +		debug("   Data Size:    %d\n", spl_image.size);
> +		debug("   Load Address: 0x%x\n", spl_image.load_addr);
> +		debug("   Entry Point:  0x%X\n", spl_image.entry_point);
> +	} else {
> +		/* Not a valid image as mkimage signature not found */
> +		printf("Error : mkimage signature not found - ih_magic = %x\n",
> +			header->ih_magic);
> +		return 1;
> +	}
> +
> +	/* Checking image type. Do any customize stuff per image type here */
> +	switch (spl_image.os) {
> +	case IH_OS_U_BOOT:
> +		debug("   Image Type:   U-Boot\n");
> +		break;
> +	default:
> +		printf("   Image Type:   Unknown (%d)\n", spl_image.os);
> +		;
> +	}
> +	return 0;
> +}

I think I don't even wanna know what's the purpose here :-)

[...]
Tom Rini - Aug. 23, 2012, 1:13 a.m.
On Thu, Aug 23, 2012 at 12:26:53AM +0200, Marek Vasut wrote:
> Dear dinguyen@altera.com,
> 
> > From: Dinh Nguyen <dinguyen@altera.com>
> > 
> > Add minimal support for Altera's SOCFPGA Cyclone 5 hardware.
> > 
> > Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> > Signed-off-by: Pavel Machek <pavel@denx.de>
> 
> [...]
> 
> Please CC albert with new arches.
> 
> > diff --git a/Makefile b/Makefile
> > index 5ce5cc3..12aa372 100644
> > --- a/Makefile
> > +++ b/Makefile
> > @@ -369,7 +369,7 @@ BOARD_SIZE_CHECK =
> >  endif
> > 
> >  # Always append ALL so that arch config.mk's can add custom ones
> > -ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map
> > +ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)u-boot.img
> > $(obj)System.map
> 
> This won't slide

You can place this into arch/arm/cpu/armv7/socfpga/config.mk (see
am33xx/config.mk or any of the others) for examples.

[snip]
> > diff --git a/arch/arm/cpu/armv7/socfpga/spl.c
> > b/arch/arm/cpu/armv7/socfpga/spl.c new file mode 100644
> > index 0000000..7bd1e2f
> > --- /dev/null
> > +++ b/arch/arm/cpu/armv7/socfpga/spl.c
> > @@ -0,0 +1,182 @@
> > + /*
> > + *  Copyright (C) 2012 Altera Corporation <www.altera.com>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> > + */
> > +
> > +#include <common.h>
> > +#include <asm/io.h>
> > +#include <asm/u-boot.h>
> > +#include <asm/utils.h>
> > +#include <asm/arch/socfpga_spl.h>
> > +#include <version.h>
> > +#include <image.h>
> > +#include <malloc.h>
> > +#include <asm/arch/reset_manager.h>
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +static u32 *boot_params_ptr;
> > +static struct spl_image_info spl_image;
> > +
> > +extern void __malloc_start, __malloc_end, __stack_start;
> > +
> > +/* Define global data structure pointer to it */
> > +static gd_t gdata __attribute__ ((section(".data")));
> > +
> > +/*
> > + * Error action
> > + */
> > +inline void hang(void)
> > +{
> > +	puts("### ERROR ### Please RESET the board ###\n");
> > +	for (;;)
> > +		;
> > +}
> > +
> > +/*
> > + * Read the mkimage signature to extract info such as entry point.
> > + * The header is generated by tools/mkimage
> > + */
> > +static unsigned long spl_parse_image_header(const struct image_header
> > *header) +{
> > +	/* checking for mkimage signature */
> > +	if (__be32_to_cpu(header->ih_magic) == IH_MAGIC) {
> > +		/* Valid image. Extract information out of header */
> > +		spl_image.size = __be32_to_cpu(header->ih_size);
> > +		spl_image.entry_point = __be32_to_cpu(header->ih_load);
> > +		spl_image.load_addr = __be32_to_cpu(header->ih_load);
> > +		spl_image.os = header->ih_os;
> > +		spl_image.name = (const char *)&header->ih_name;
> > +		spl_image.crc = __be32_to_cpu(header->ih_dcrc);
> > +		debug("Subsequent boot image info\n");
> > +		debug("   Image Name:   %.*s\n", IH_NMLEN, spl_image.name);
> > +		debug("   Data Size:    %d\n", spl_image.size);
> > +		debug("   Load Address: 0x%x\n", spl_image.load_addr);
> > +		debug("   Entry Point:  0x%X\n", spl_image.entry_point);
> > +	} else {
> > +		/* Not a valid image as mkimage signature not found */
> > +		printf("Error : mkimage signature not found - ih_magic = %x\n",
> > +			header->ih_magic);
> > +		return 1;
> > +	}
> > +
> > +	/* Checking image type. Do any customize stuff per image type here */
> > +	switch (spl_image.os) {
> > +	case IH_OS_U_BOOT:
> > +		debug("   Image Type:   U-Boot\n");
> > +		break;
> > +	default:
> > +		printf("   Image Type:   Unknown (%d)\n", spl_image.os);
> > +		;
> > +	}
> > +	return 0;
> > +}
> 
> I think I don't even wanna know what's the purpose here :-)

It's the omap-common/spl.c code with the bits for IH_OS_LINUX taken out
:)  Can you please re-do your series on top of the SPL series I just
posted that provides a common SPL framework?  Thanks!
Pavel Machek - Aug. 23, 2012, 10:43 a.m.
Hi!

> > > diff --git a/Makefile b/Makefile
> > > index 5ce5cc3..12aa372 100644
> > > --- a/Makefile
> > > +++ b/Makefile
> > > @@ -369,7 +369,7 @@ BOARD_SIZE_CHECK =
> > >  endif
> > > 
> > >  # Always append ALL so that arch config.mk's can add custom ones
> > > -ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map
> > > +ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)u-boot.img
> > > $(obj)System.map
> > 
> > This won't slide
> 
> You can place this into arch/arm/cpu/armv7/socfpga/config.mk (see
> am33xx/config.mk or any of the others) for examples.

Thanks.

> > > +static unsigned long spl_parse_image_header(const struct image_header
> > > *header) +{
> > > +	/* checking for mkimage signature */
> > > +	if (__be32_to_cpu(header->ih_magic) == IH_MAGIC) {
> > > +		/* Valid image. Extract information out of header */
> > > +		spl_image.size = __be32_to_cpu(header->ih_size);
> > > +		spl_image.entry_point = __be32_to_cpu(header->ih_load);
> > > +		spl_image.load_addr = __be32_to_cpu(header->ih_load);
> > > +		spl_image.os = header->ih_os;
> > > +		spl_image.name = (const char *)&header->ih_name;
> > > +		spl_image.crc = __be32_to_cpu(header->ih_dcrc);
> > > +		debug("Subsequent boot image info\n");
> > > +		debug("   Image Name:   %.*s\n", IH_NMLEN, spl_image.name);
> > > +		debug("   Data Size:    %d\n", spl_image.size);
> > > +		debug("   Load Address: 0x%x\n", spl_image.load_addr);
> > > +		debug("   Entry Point:  0x%X\n", spl_image.entry_point);
> > > +	} else {
> > > +		/* Not a valid image as mkimage signature not found */
> > > +		printf("Error : mkimage signature not found - ih_magic = %x\n",
> > > +			header->ih_magic);
> > > +		return 1;
> > > +	}
> > > +
> > > +	/* Checking image type. Do any customize stuff per image type here */
> > > +	switch (spl_image.os) {
> > > +	case IH_OS_U_BOOT:
> > > +		debug("   Image Type:   U-Boot\n");
> > > +		break;
> > > +	default:
> > > +		printf("   Image Type:   Unknown (%d)\n", spl_image.os);
> > > +		;
> > > +	}
> > > +	return 0;
> > > +}
> > 
> > I think I don't even wanna know what's the purpose here :-)
> 
> It's the omap-common/spl.c code with the bits for IH_OS_LINUX taken out
> :)  Can you please re-do your series on top of the SPL series I just
> posted that provides a common SPL framework?  Thanks!

I'll take a look. OTOH, ammount of code duplication here is quite low,
and redoing it on top of SPL series will mean delaying merge, right?
									Pavel
Stefan Roese - Aug. 23, 2012, 11:18 a.m.
Hi Pavel,

On 08/23/2012 12:43 PM, Pavel Machek wrote:
>>>> +static unsigned long spl_parse_image_header(const struct image_header
>>>> *header) +{
>>>> +	/* checking for mkimage signature */
>>>> +	if (__be32_to_cpu(header->ih_magic) == IH_MAGIC) {
>>>> +		/* Valid image. Extract information out of header */
>>>> +		spl_image.size = __be32_to_cpu(header->ih_size);
>>>> +		spl_image.entry_point = __be32_to_cpu(header->ih_load);
>>>> +		spl_image.load_addr = __be32_to_cpu(header->ih_load);
>>>> +		spl_image.os = header->ih_os;
>>>> +		spl_image.name = (const char *)&header->ih_name;
>>>> +		spl_image.crc = __be32_to_cpu(header->ih_dcrc);
>>>> +		debug("Subsequent boot image info\n");
>>>> +		debug("   Image Name:   %.*s\n", IH_NMLEN, spl_image.name);
>>>> +		debug("   Data Size:    %d\n", spl_image.size);
>>>> +		debug("   Load Address: 0x%x\n", spl_image.load_addr);
>>>> +		debug("   Entry Point:  0x%X\n", spl_image.entry_point);
>>>> +	} else {
>>>> +		/* Not a valid image as mkimage signature not found */
>>>> +		printf("Error : mkimage signature not found - ih_magic = %x\n",
>>>> +			header->ih_magic);
>>>> +		return 1;
>>>> +	}
>>>> +
>>>> +	/* Checking image type. Do any customize stuff per image type here */
>>>> +	switch (spl_image.os) {
>>>> +	case IH_OS_U_BOOT:
>>>> +		debug("   Image Type:   U-Boot\n");
>>>> +		break;
>>>> +	default:
>>>> +		printf("   Image Type:   Unknown (%d)\n", spl_image.os);
>>>> +		;
>>>> +	}
>>>> +	return 0;
>>>> +}
>>>
>>> I think I don't even wanna know what's the purpose here :-)
>>
>> It's the omap-common/spl.c code with the bits for IH_OS_LINUX taken out
>> :)  Can you please re-do your series on top of the SPL series I just
>> posted that provides a common SPL framework?  Thanks!
> 
> I'll take a look. OTOH, ammount of code duplication here is quite low,
> and redoing it on top of SPL series will mean delaying merge, right?

Yes, that might happen. But we learned in the past that if we don't try
to do such code consolidations right from the beginning, it won't happen
at all (most of the time). So I'm also in favor of using the common SPL
framework now. Please take a look at Tom Rini's v3 series:

http://www.mail-archive.com/u-boot@lists.denx.de/msg91405.html

I also based my powerpc SPL NOR flash booting series on it:

http://www.mail-archive.com/u-boot@lists.denx.de/msg91443.html

Thanks,
Stefan
Tom Rini - Aug. 24, 2012, 7:18 p.m.
On 08/23/2012 03:43 AM, Pavel Machek wrote:

[snip]
>> It's the omap-common/spl.c code with the bits for IH_OS_LINUX taken out
>> :)  Can you please re-do your series on top of the SPL series I just
>> posted that provides a common SPL framework?  Thanks!
> 
> I'll take a look. OTOH, ammount of code duplication here is quite low,
> and redoing it on top of SPL series will mean delaying merge, right?

My hope is that since I got the SPL patches posted in time we can get
them in for v2012.10 so no, this will only help your chances :)
Pavel Machek - Aug. 25, 2012, 9:03 a.m.
Hi!

> [snip]
> >> It's the omap-common/spl.c code with the bits for IH_OS_LINUX taken out
> >> :)  Can you please re-do your series on top of the SPL series I just
> >> posted that provides a common SPL framework?  Thanks!
> > 
> > I'll take a look. OTOH, ammount of code duplication here is quite low,
> > and redoing it on top of SPL series will mean delaying merge, right?
> 
> My hope is that since I got the SPL patches posted in time we can get
> them in for v2012.10 so no, this will only help your chances :)

Ok, but how do I get them applied?

I tried applying them over:

commit e66443fdb5355e68cfdbbdd37248c4b7eb4968f5
Author: Scott Wood <scottwood@freescale.com>
Date:   Tue Aug 14 01:44:29 2012 +0000

    Makefile: fix HAVE_VENDOR_COMMON_LIB
    
    Commit 8b5a02640adf77301f943e8754992c50df004e8a ("Makefile:
    cosmetic:
    optimize usage of LIBS-y") broke the build of boards that have a
    board
    vendor "common" directory, by introducing a space between "LIBS-"
    and
    "y".
    
    Signed-off-by: Scott Wood <scottwood@freescale.com>
    Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
    Acked-by: Kim Phillips <kim.phillips@freescale.com>

and am getting errors:

|index b314ed7..d8ade27 100644
|--- a/common/spl/spl.c
|+++ b/common/spl/spl.c
--------------------------
File to patch: ^C

Is there git to pull? One big patch for easier application?

Thanks,

									Pavel
Pavel Machek - Aug. 25, 2012, 11:56 a.m.
Hi!

> [snip]
> >> It's the omap-common/spl.c code with the bits for IH_OS_LINUX taken out
> >> :)  Can you please re-do your series on top of the SPL series I just
> >> posted that provides a common SPL framework?  Thanks!
> > 
> > I'll take a look. OTOH, ammount of code duplication here is quite low,
> > and redoing it on top of SPL series will mean delaying merge, right?
> 
> My hope is that since I got the SPL patches posted in time we can get
> them in for v2012.10 so no, this will only help your chances :)

Hopefully.

Some observations:

Not sure what to do with CONFIG_SPL_STACK: altera was just using
symbol from linker script. Is there way to keep it like that? I'd hate
to invent magic constant.

Same issue with CONFIG_SYS_SPL_MALLOC_START... I was doing:

        /* setup MALLOC after clocks going faster */
	mem_malloc_init((ulong) &__malloc_start,
					(&__malloc_end -
	&__malloc_start));

I guess defines allow me to keep my definition. Good.

spl_parse_image_header(): We have "modern" system, we'd prefer not to
do
                /* Signature not found - assume u-boot.bin */
...but to hang in that case, in order not to jump to random code.

Ok, I should have something publishable, soon ;-).
									Pavel
Tom Rini - Aug. 27, 2012, 3:43 p.m.
On 08/25/2012 04:56 AM, Pavel Machek wrote:
> Hi!
> 
>> [snip]
>>>> It's the omap-common/spl.c code with the bits for IH_OS_LINUX taken out
>>>> :)  Can you please re-do your series on top of the SPL series I just
>>>> posted that provides a common SPL framework?  Thanks!
>>>
>>> I'll take a look. OTOH, ammount of code duplication here is quite low,
>>> and redoing it on top of SPL series will mean delaying merge, right?
>>
>> My hope is that since I got the SPL patches posted in time we can get
>> them in for v2012.10 so no, this will only help your chances :)
> 
> Hopefully.
> 
> Some observations:
> 
> Not sure what to do with CONFIG_SPL_STACK: altera was just using
> symbol from linker script. Is there way to keep it like that? I'd hate
> to invent magic constant.

Well, lets think about this.  Previously, everyone has been saying "use
this spot in SRAM" or "use this spot in DRAM (which has been setup
previously)".  But I think you should be able to do
#define CONFIG_SPL_STACK __linker_symbol and be done with it.

> Same issue with CONFIG_SYS_SPL_MALLOC_START... I was doing:
> 
>         /* setup MALLOC after clocks going faster */
> 	mem_malloc_init((ulong) &__malloc_start,
> 					(&__malloc_end -
> 	&__malloc_start));
> 
> I guess defines allow me to keep my definition. Good.

Should be fine, yes.

> spl_parse_image_header(): We have "modern" system, we'd prefer not to
> do
>                 /* Signature not found - assume u-boot.bin */
> ...but to hang in that case, in order not to jump to random code.
> 
> Ok, I should have something publishable, soon ;-).

The only reason I like the assumption idea is that I've already seen at
least one distribution ship new MLO (based on SPL) and u-boot.bin rather
than u-boot.img for their beagleboard images.
Pavel Machek - Aug. 29, 2012, 12:30 p.m.
Hi!

> > I'll take a look. OTOH, ammount of code duplication here is quite low,
> > and redoing it on top of SPL series will mean delaying merge, right?
> 
> Yes, that might happen. But we learned in the past that if we don't try
> to do such code consolidations right from the beginning, it won't happen
> at all (most of the time). So I'm also in favor of using the common SPL
> framework now. Please take a look at Tom Rini's v3 series:

No problem, it really looks much better on top of Tom's patches.

									Pavel
Stefan Roese - Aug. 29, 2012, 12:32 p.m.
Hi Pavel,

On 08/29/2012 02:30 PM, Pavel Machek wrote:
> Hi!
> 
>>> I'll take a look. OTOH, ammount of code duplication here is quite low,
>>> and redoing it on top of SPL series will mean delaying merge, right?
>>
>> Yes, that might happen. But we learned in the past that if we don't try
>> to do such code consolidations right from the beginning, it won't happen
>> at all (most of the time). So I'm also in favor of using the common SPL
>> framework now. Please take a look at Tom Rini's v3 series:
> 
> No problem, it really looks much better on top of Tom's patches.

Great. Thanks for the extra work.

Cheers,
Stefan

Patch

diff --git a/MAINTAINERS b/MAINTAINERS
index c5a6f2f..df48dea 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -765,6 +765,11 @@  Nagendra T S  <nagendra@mistralsolutions.com>
 
    am3517_crane    ARM ARMV7 (AM35x SoC)
 
+Dinh Nguyen <dinguyen@altera.com>
+Chin Liang See <clsee@altera.com>
+
+	socfpga		socfpga_cyclone5
+
 Kyungmin Park <kyungmin.park@samsung.com>
 
 	apollon		ARM1136EJS
diff --git a/Makefile b/Makefile
index 5ce5cc3..12aa372 100644
--- a/Makefile
+++ b/Makefile
@@ -369,7 +369,7 @@  BOARD_SIZE_CHECK =
 endif
 
 # Always append ALL so that arch config.mk's can add custom ones
-ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map
+ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)u-boot.img $(obj)System.map
 
 ALL-$(CONFIG_NAND_U_BOOT) += $(obj)u-boot-nand.bin
 ALL-$(CONFIG_ONENAND_U_BOOT) += $(obj)u-boot-onenand.bin
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile
new file mode 100644
index 0000000..e4c1213
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -0,0 +1,51 @@ 
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2012 Altera Corporation <www.altera.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+
+include $(TOPDIR)/config.mk
+
+LIB	=  $(obj)lib$(SOC).o
+
+SOBJS	:= lowlevel_init.o
+COBJS-y	:= reset_manager.o sdram.o timer.o
+COBJS-$(CONFIG_SPL_BUILD) += spl.o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all:	 $(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S
new file mode 100644
index 0000000..815073e
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S
@@ -0,0 +1,79 @@ 
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <config.h>
+#include <version.h>
+
+/* Save the parameter pass in by previous boot loader */
+.global save_boot_params
+save_boot_params:
+	/* save the parameter here */
+
+	/*
+	 * Setup stack for exception, which is located
+	 * at the end of on-chip RAM. We don't expect exception prior to
+	 * relocation and if that happens, we won't worry -- it will overide
+	 * global data region as the code will goto reset. After relocation,
+	 * this region won't be used by other part of program.
+	 * Hence it is safe.
+	 */
+	ldr	r0, =CONFIG_SYS_INIT_RAM_ADDR
+	ldr	r1, =CONFIG_SYS_INIT_RAM_SIZE
+	add	r0, r0, r1
+	ldr	r1, =IRQ_STACK_START_IN
+	str	r0, [r1]
+
+	bx	lr
+
+
+/* Set up the platform, once the cpu has been initialized */
+.globl lowlevel_init
+lowlevel_init:
+
+	/* Remap */
+#ifdef CONFIG_SPL_BUILD
+	/*
+	 * SPL : configure the remap (L3 NIC-301 GPV)
+	 * so the on-chip RAM at lower memory instead ROM.
+	 */
+	ldr	r0, =SOCFPGA_L3REGS_ADDRESS
+	mov	r1, #0x19
+	str	r1, [r0]
+#else
+	/*
+	 * U-Boot : configure the remap (L3 NIC-301 GPV)
+	 * so the SDRAM at lower memory instead on-chip RAM.
+	 */
+	ldr	r0, =SOCFPGA_L3REGS_ADDRESS
+	mov	r1, #0x2
+	str	r1, [r0]
+
+	/* Private components security */
+
+	/*
+	 * U-Boot : configure private timer, global timer and cpu
+	 * component access as non secure for kernel stage (as required
+	 * by kernel)
+	 */
+	mrc	p15,4,r0,c15,c0,0
+	add	r1, r0, #0x54
+	ldr	r2, [r1]
+	orr	r2, r2, #0xff
+	orr	r2, r2, #0xf00
+	str	r2, [r1]
+#endif	/* #ifdef CONFIG_SPL_BUILD */
+	mov	pc, lr
diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c
new file mode 100644
index 0000000..b0fa211
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c
@@ -0,0 +1,45 @@ 
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/reset_manager.h>
+
+static const struct socfpga_reset_manager *reset_manager_base =
+		(void *)SOCFPGA_RSTMGR_ADDRESS;
+
+/*
+ * Write the reset manager register to cause reset
+ */
+void reset_cpu(ulong addr)
+{
+	/* request a warm reset */
+	writel(RSTMGR_CTRL_SWWARMRSTREQ_LSB, &reset_manager_base->ctrl);
+	/* infinite loop here as watchdog will trigger and reset
+	 * the processor */
+	while (1)
+		;
+}
+
+/*
+ * Release peripherals from reset based on handoff
+ */
+void reset_deassert_peripherals_handoff(void)
+{
+	unsigned int val = 0;
+	writel(val, &reset_manager_base->per_mod_reset);
+}
diff --git a/arch/arm/cpu/armv7/socfpga/sdram.c b/arch/arm/cpu/armv7/socfpga/sdram.c
new file mode 100644
index 0000000..6714983
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/sdram.c
@@ -0,0 +1,26 @@ 
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c
new file mode 100644
index 0000000..7bd1e2f
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/spl.c
@@ -0,0 +1,182 @@ 
+ /*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/u-boot.h>
+#include <asm/utils.h>
+#include <asm/arch/socfpga_spl.h>
+#include <version.h>
+#include <image.h>
+#include <malloc.h>
+#include <asm/arch/reset_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 *boot_params_ptr;
+static struct spl_image_info spl_image;
+
+extern void __malloc_start, __malloc_end, __stack_start;
+
+/* Define global data structure pointer to it */
+static gd_t gdata __attribute__ ((section(".data")));
+
+/*
+ * Error action
+ */
+inline void hang(void)
+{
+	puts("### ERROR ### Please RESET the board ###\n");
+	for (;;)
+		;
+}
+
+/*
+ * Read the mkimage signature to extract info such as entry point.
+ * The header is generated by tools/mkimage
+ */
+static unsigned long spl_parse_image_header(const struct image_header *header)
+{
+	/* checking for mkimage signature */
+	if (__be32_to_cpu(header->ih_magic) == IH_MAGIC) {
+		/* Valid image. Extract information out of header */
+		spl_image.size = __be32_to_cpu(header->ih_size);
+		spl_image.entry_point = __be32_to_cpu(header->ih_load);
+		spl_image.load_addr = __be32_to_cpu(header->ih_load);
+		spl_image.os = header->ih_os;
+		spl_image.name = (const char *)&header->ih_name;
+		spl_image.crc = __be32_to_cpu(header->ih_dcrc);
+		debug("Subsequent boot image info\n");
+		debug("   Image Name:   %.*s\n", IH_NMLEN, spl_image.name);
+		debug("   Data Size:    %d\n", spl_image.size);
+		debug("   Load Address: 0x%x\n", spl_image.load_addr);
+		debug("   Entry Point:  0x%X\n", spl_image.entry_point);
+	} else {
+		/* Not a valid image as mkimage signature not found */
+		printf("Error : mkimage signature not found - ih_magic = %x\n",
+			header->ih_magic);
+		return 1;
+	}
+
+	/* Checking image type. Do any customize stuff per image type here */
+	switch (spl_image.os) {
+	case IH_OS_U_BOOT:
+		debug("   Image Type:   U-Boot\n");
+		break;
+	default:
+		printf("   Image Type:   Unknown (%d)\n", spl_image.os);
+		;
+	}
+	return 0;
+}
+
+static void spl_ram_load_image(void)
+{
+	u32 err;
+	const struct image_header *header;
+
+	/* get the header */
+	/* it will point to a address defined by handoff which
+	will tell where the image located inside the flash. For now,
+	it will temporary fixed to address pointed by U-Boot */
+	header = (struct image_header *)
+		(CONFIG_SYS_TEXT_BASE -	sizeof(struct image_header));
+
+	err = spl_parse_image_header(header);
+	if (err) {
+		puts("SPL : RAM image header error\n");
+		hang();
+	}
+}
+
+/*
+ * Jump to subseqeuent bootloaders / U-boot
+ */
+static void jump_to_image_no_args(void)
+{
+	typedef void (*image_entry_noargs_t)(u32 *)__attribute__ ((noreturn));
+	image_entry_noargs_t image_entry =
+			(image_entry_noargs_t) spl_image.entry_point;
+	/* Pass the saved boot_params from rom code */
+	u32 boot_params_ptr_addr = (u32)&boot_params_ptr;
+
+	puts("\nLeaving SPL ...\n");
+	image_entry((u32 *)boot_params_ptr_addr);
+}
+void jump_to_image_no_args(void) __attribute__ ((noreturn));
+
+
+/*
+ * Console Initialization
+ */
+static void spl_console_init(void)
+{
+	gd->flags |= GD_FLG_RELOC;
+	gd->baudrate = CONFIG_BAUDRATE;
+
+	/* serial communications setup */
+	serial_init();
+	gd->have_console = 1;
+}
+
+/*
+ * Board initialization prior bss clearance
+ * Do note below concerns when inserting your function here.
+ * Please refer to README for more details.
+
+ * Initialized global data (data segment) is read-only. Do not attempt
+	to write it.
+
+ * Do not use any uninitialized global data (or implicitely initialized
+	as zero data - BSS segment) at all - this is undefined, initiali-
+	zation is performed later (when relocating to RAM).
+
+ * Stack space is very limited. Avoid big data buffers or things like
+	that.
+ */
+void board_init_f(ulong dummy)
+{
+	/* Will clear bss then jump back to function board_init_r */
+	relocate_code((ulong) &__stack_start, &gdata, CONFIG_SPL_TEXT_BASE);
+}
+
+/*
+ * Board initialization after bss clearance
+ */
+void board_init_r(gd_t *id, ulong dummy)
+{
+	gd = &gdata;
+
+	/* init timer for enabling delay function */
+	timer_init();
+
+	/* de-assert reset for peripherals and bridges based on handoff */
+	reset_deassert_peripherals_handoff();
+
+	/* enable console uart printing */
+	spl_console_init();
+
+	/* setup MALLOC after clocks going faster */
+	mem_malloc_init((ulong) &__malloc_start,
+			(&__malloc_end - &__malloc_start));
+
+	puts("SPL Boot from RAM\n");
+	spl_ram_load_image();
+
+	/* jump to subsequent bootloader */
+	jump_to_image_no_args();
+}
diff --git a/arch/arm/cpu/armv7/socfpga/timer.c b/arch/arm/cpu/armv7/socfpga/timer.c
new file mode 100644
index 0000000..1fb3a83
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/timer.c
@@ -0,0 +1,118 @@ 
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch-armv7/systimer.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#undef SYSTIMER_BASE
+#define SYSTIMER_BASE	CONFIG_SYS_TIMERBASE /* Timer 0 base */
+
+static struct systimer *systimer_base = (struct systimer *)SYSTIMER_BASE;
+
+static inline unsigned long long time_to_tick()
+{
+	return CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ;
+}
+
+int timer_init(void)
+{
+	writel(TIMER_LOAD_VAL, &systimer_base->timer0load);
+	writel(TIMER_LOAD_VAL, &systimer_base->timer0value);
+	writel((readl((&systimer_base->timer0control)) | 0x3),
+		(&systimer_base->timer0control));
+
+	reset_timer();
+	return 0;
+}
+
+static u32 read_timer(void)
+{
+	return readl(&systimer_base->timer0value);
+}
+
+void __udelay(unsigned long usec)
+{
+	unsigned long now, last;
+	/*
+	 * get the tmo value based on timer clock speed
+	 * tmo = delay required / period of timer clock
+	 */
+	long tmo = usec * time_to_tick();
+
+	last = read_timer();
+	while (tmo > 0) {
+		now = read_timer();
+		if (last >= now)
+			/* normal mode (non roll) */
+			tmo -= last - now;
+		else
+			/* we have overflow of the count down timer */
+			tmo -= TIMER_LOAD_VAL - last + now;
+		last = now;
+	}
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+ulong get_timer_masked(void)
+{
+	/* current tick value */
+	ulong now = read_timer() / time_to_tick();
+	if (gd->lastinc >= now) {
+		/* normal mode (non roll) */
+		/* move stamp forward with absolute diff ticks */
+		gd->tbl += gd->lastinc - now;
+	} else {
+		/* we have overflow of the count down timer */
+		gd->tbl += TIMER_LOAD_VAL - gd->lastinc + now;
+	}
+	gd->lastinc = now;
+	return gd->tbl;
+}
+
+void reset_timer(void)
+{
+	gd->lastinc = read_timer() / time_to_tick();
+	gd->tbl = 0;
+}
+
+ulong get_timer_count_masked(void)
+{
+	ulong now = read_timer();
+	if (gd->lastinc >= now) {
+		/* normal mode (non roll) */
+		/* move stamp forward with absolute diff ticks */
+		gd->tbl += gd->lastinc - now;
+	} else {
+		/* we have overflow of the count down timer */
+		gd->tbl += TIMER_LOAD_VAL - gd->lastinc + now;
+	}
+	gd->lastinc = now;
+	return gd->tbl;
+}
+
+ulong get_timer_count(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
diff --git a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
new file mode 100644
index 0000000..de74341
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
@@ -0,0 +1,60 @@ 
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	:
+	{
+		arch/arm/cpu/armv7/start.o	(.text)
+		*(.text*)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : { *(SORT_BY_ALIGNMENT(.data*)) }
+
+	. = ALIGN(4);
+	__image_copy_end = .;
+	_end = .;
+
+	.bss : {
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	}
+
+	. = . + 4;
+	. = ALIGN(8);
+	__malloc_start = .;
+	. = . + CONFIG_SPL_MALLOC_SIZE;
+	__malloc_end = .;
+
+	. = . + 4;
+	. = . + CONFIG_SPL_STACK_SIZE;
+	. = ALIGN(8);
+	__stack_start = .;
+}
diff --git a/arch/arm/include/asm/arch-socfpga/reset_config.h b/arch/arm/include/asm/arch-socfpga/reset_config.h
new file mode 100644
index 0000000..e69de29
diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h
new file mode 100644
index 0000000..d9d2c1c
--- /dev/null
+++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h
@@ -0,0 +1,37 @@ 
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef	_RESET_MANAGER_H_
+#define	_RESET_MANAGER_H_
+
+void reset_cpu(ulong addr);
+void reset_deassert_peripherals_handoff(void);
+
+struct socfpga_reset_manager {
+	u32	padding1;
+	u32	ctrl;
+	u32	padding2;
+	u32	padding3;
+	u32	mpu_mod_reset;
+	u32	per_mod_reset;
+	u32	per2_mod_reset;
+	u32	brg_mod_reset;
+};
+
+#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
+
+#endif /* _RESET_MANAGER_H_ */
diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
new file mode 100644
index 0000000..f353eb2
--- /dev/null
+++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
@@ -0,0 +1,27 @@ 
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SOCFPGA_BASE_ADDRS_H_
+#define _SOCFPGA_BASE_ADDRS_H_
+
+#define SOCFPGA_L3REGS_ADDRESS 0xff800000
+#define SOCFPGA_UART0_ADDRESS 0xffc02000
+#define SOCFPGA_UART1_ADDRESS 0xffc03000
+#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
+#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
+
+#endif /* _SOCFPGA_BASE_ADDRS_H_ */
diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_spl.h b/arch/arm/include/asm/arch-socfpga/socfpga_spl.h
new file mode 100644
index 0000000..ee4b6d3
--- /dev/null
+++ b/arch/arm/include/asm/arch-socfpga/socfpga_spl.h
@@ -0,0 +1,30 @@ 
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef	_SOCPFGA_SPL_H_
+#define	_SOCPFGA_SPL_H_
+
+struct spl_image_info {
+	const char *name;
+	u8 os;
+	u32 load_addr;
+	u32 entry_point;
+	u32 size;
+	u32 crc;
+};
+
+#endif /* _SOCPFGA_SPL_H_ */
diff --git a/board/altera/socfpga_cyclone5/Makefile b/board/altera/socfpga_cyclone5/Makefile
new file mode 100644
index 0000000..43bbc37
--- /dev/null
+++ b/board/altera/socfpga_cyclone5/Makefile
@@ -0,0 +1,50 @@ 
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= socfpga_cyclone5.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/altera/socfpga_cyclone5/socfpga_cyclone5.c b/board/altera/socfpga_cyclone5/socfpga_cyclone5.c
new file mode 100644
index 0000000..1248e3d
--- /dev/null
+++ b/board/altera/socfpga_cyclone5/socfpga_cyclone5.c
@@ -0,0 +1,97 @@ 
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/io.h>
+
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void show_boot_progress(int progress)
+{
+	debug("Boot reached stage %d\n", progress);
+}
+
+static inline void delay(unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+		"subs %0, %1, #1\n"
+		"bne 1b" : "=r" (loops) : "0" (loops));
+}
+
+/*
+ * Print CPU information
+ */
+int print_cpuinfo(void)
+{
+	puts("CPU   : Altera SOCFPGA Platform\n");
+	return 0;
+}
+
+/*
+ * Print Board information
+ */
+int checkboard(void)
+{
+	puts("BOARD : Altera SOCFPGA Cyclone5 Board\n");
+	return 0;
+}
+
+/*
+ * Initialization function which happen at early stage of c code
+ */
+int board_early_init_f(void)
+{
+	return 0;
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+	icache_enable();
+	return 0;
+}
+
+/*
+ * miscellaneous platform dependent initialisations
+ */
+int misc_init_r(void)
+{
+	/* Set to "n" for not verifying the uImage */
+	setenv("verify", "n");
+	return 0;
+}
+
+#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
+int overwrite_console(void)
+{
+	return 0;
+}
+#endif
+
+/*
+ * DesignWare Ethernet initialization
+ */
+/* We know all the init functions have been run now */
+int board_eth_init(bd_t *bis)
+{
+	return 0;
+}
diff --git a/boards.cfg b/boards.cfg
index fdb84ad..1b5c860 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -261,6 +261,7 @@  seaboard                     arm         armv7       seaboard            nvidia
 ventana                      arm         armv7       ventana             nvidia         tegra2
 whistler                     arm         armv7       whistler            nvidia         tegra2
 u8500_href                   arm         armv7       u8500               st-ericsson    u8500
+socfpga_cyclone5              arm         armv7      socfpga_cyclone5    altera		    socfpga
 actux1_4_16                  arm         ixp         actux1              -              -           actux1:FLASH2X2
 actux1_4_32                  arm         ixp         actux1              -              -           actux1:FLASH2X2,RAM_32MB
 actux1_8_16                  arm         ixp         actux1              -              -           actux1:FLASH1X8
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
new file mode 100644
index 0000000..29aa9da
--- /dev/null
+++ b/include/configs/socfpga_cyclone5.h
@@ -0,0 +1,240 @@ 
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/socfpga_base_addrs.h>
+
+/*
+ * High level configuration
+ */
+
+#define CONFIG_ARMV7
+#define CONFIG_L2_OFF
+#define CONFIG_SYS_DCACHE_OFF
+#undef CONFIG_USE_IRQ
+
+#define CONFIG_MISC_INIT_R
+#define CONFIG_SINGLE_BOOTLOADER
+#define CONFIG_SOCFPGA
+
+#define CONFIG_SYS_TEXT_BASE		0x08000040
+#define V_NS16550_CLK			1000000
+#define CONFIG_BAUDRATE			57600
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_TIMER_CLOCK_KHZ		2400
+#define CONFIG_SYS_LOAD_ADDR		0x7fc0
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		256
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT		"SOCFPGA_CYCLONE5 # "
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/*
+ * Display CPU and Board Info
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/*
+ * Enable early stage initialization at C environment
+ */
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* flat device tree */
+#define CONFIG_OF_LIBFDT
+/* skip updating the FDT blob */
+#define CONFIG_FDT_BLOB_SKIP_UPDATE
+/* Initial Memory map size for Linux, minus 4k alignment for DFT blob */
+#define CONFIG_SYS_BOOTMAPSZ		((256*1024*1024) - (4*1024))
+
+/*
+ * Memory allocation (MALLOC)
+ */
+/* Room required on the stack for the environment data */
+#define CONFIG_ENV_SIZE			1024
+/* Size of DRAM reserved for malloc() use */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+
+/*
+ * Stack sizes
+ * The stack sizes are set up in start.S using the settings below
+ */
+/* regular stack */
+#define CONFIG_STACKSIZE		(128 << 10)
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack */
+#define CONFIG_STACKSIZE_IRQ		(4 << 10)
+/* FIQ stack */
+#define CONFIG_STACKSIZE_FIQ		(4 << 10)
+#endif
+/* SP location before relocation, must use scratch RAM */
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFFFF0000
+/* Reserving 0x100 space at back of scratch RAM for debug info */
+#define CONFIG_SYS_INIT_RAM_SIZE	(0x10000 - 0x100)
+/* Stack pointer prior relocation, must situated at on-chip RAM */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_SYS_NO_FLASH
+#include <config_cmd_default.h>
+/* FAT file system support */
+#define CONFIG_CMD_FAT
+
+
+/*
+ * Misc
+ */
+#define CONFIG_DOS_PARTITION            1
+
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_PARTITIONS
+#endif
+
+/*
+ * Environment setup
+ */
+
+/* Delay before automatically booting the default image */
+#define CONFIG_BOOTDELAY		3
+/* Enable auto completion of commands using TAB */
+#define CONFIG_AUTO_COMPLETE
+/* use "hush" command parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_CMD_RUN
+
+#define CONFIG_BOOTCOMMAND "run ramboot"
+
+/*
+ * arguments passed to the bootm command. The value of
+ * CONFIG_BOOTARGS goes into the environment value "bootargs".
+ * Do note the value will overide also the chosen node in FDT blob.
+ */
+#define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M@0x0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr= " MK_STR(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
+		"bootm ${loadaddr} - ${fdt_addr}\0" \
+	"bootimage=uImage\0" \
+	"fdt_addr=100\0" \
+	"fsloadcmd=ext2load\0" \
+		"bootm ${loadaddr} - ${fdt_addr}\0" \
+	"qspiroot=/dev/mtdblock0\0" \
+	"qspirootfstype=jffs2\0" \
+	"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+		" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
+		"bootm ${loadaddr} - ${fdt_addr}\0"
+
+/* using environment setting for stdin, stdout, stderr */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+/* Enable the call to overwrite_console() */
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+/* Enable overwrite of previous console environment settings */
+#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+/* max number of command args	 */
+#define CONFIG_SYS_MAXARGS		16
+
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * SDRAM Memory Map
+ */
+/* We have 1 bank of DRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+/* SDRAM Bank #1 */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+/* SDRAM memory size */
+#define PHYS_SDRAM_1_SIZE		0x80000000
+
+#define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_START	0x00000000
+#define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1_SIZE
+
+/*
+ * NS16550 Configuration
+ */
+#define UART0_BASE			SOCFPGA_UART0_ADDRESS
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
+#define CONFIG_CONS_INDEX               1
+#define CONFIG_SYS_NS16550_COM1		UART0_BASE
+
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+
+/*
+ * FLASH
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * L4 OSC1 Timer 0
+ */
+/* This timer use eosc1 where the clock frequency is fixed
+ * throughout any condition */
+#define CONFIG_SYS_TIMERBASE		SOCFPGA_OSC1TIMER0_ADDRESS
+
+/* reload value when timer count to zero */
+#define TIMER_LOAD_VAL			0xFFFFFFFF
+
+#define CONFIG_ENV_IS_NOWHERE
+
+/*
+ * SPL "Second Program Loader" aka Initial Software
+ */
+
+/* Enable building of SPL globally */
+#define CONFIG_SPL
+
+/* TEXT_BASE for linking the SPL binary */
+#define CONFIG_SPL_TEXT_BASE		0xFFFF0000
+
+/* Stack size for SPL */
+#define CONFIG_SPL_STACK_SIZE		(4 * 1024)
+
+/* MALLOC size for SPL */
+#define CONFIG_SPL_MALLOC_SIZE		(5 * 1024)
+
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+#define CHUNKSZ_CRC32			(1 * 1024)
+
+#define CONFIG_CRC32_VERIFY
+
+/* Linker script for SPL */
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
+
+/* Support for common/libcommon.o in SPL binary */
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+/* Support for lib/libgeneric.o in SPL binary */
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+
+#endif	/* __CONFIG_H */