diff mbox

[MIPS] add new peephole for 74k dspr2

Message ID 502D0DF4.3070302@codesourcery.com
State New
Headers show

Commit Message

Sandra Loosemore Aug. 16, 2012, 3:12 p.m. UTC 
This patch adds a peephole optimization to use a clever trick to 
zero-initialize the two halves of an accumulator register with one 
instruction instead of a mtlo/mthi pair.  OK to check in?

-Sandra

2012-08-16  Sandra Loosemore  <sandra@codesourcery.com>
	    Julian Brown  <julian@codesourcery.com>
	    MIPS Technologies, Inc.

	gcc/
	* config/mips/mips-dspr2.md (UNSPEC_ACC_INIT): Declare.
	(mult peephole2): Add peephole that converts
	"mtlo $ac[1-3],$0; mthi $ac[1-3],$0" into
         "mult $ac[1-3],$0,$0".
	(*mips_acc_init): New insn for above.

Comments

Richard Sandiford Aug. 19, 2012, 5:22 p.m. UTC | #1 
Sandra Loosemore <sandra@codesourcery.com> writes:
> This patch adds a peephole optimization to use a clever trick to 
> zero-initialize the two halves of an accumulator register with one 
> instruction instead of a mtlo/mthi pair.  OK to check in?
>
> -Sandra
>
> 2012-08-16  Sandra Loosemore  <sandra@codesourcery.com>
> 	    Julian Brown  <julian@codesourcery.com>
> 	    MIPS Technologies, Inc.
>
> 	gcc/
> 	* config/mips/mips-dspr2.md (UNSPEC_ACC_INIT): Declare.
> 	(mult peephole2): Add peephole that converts
> 	"mtlo $ac[1-3],$0; mthi $ac[1-3],$0" into
>          "mult $ac[1-3],$0,$0".
> 	(*mips_acc_init): New insn for above.

Not sure whether a peephole is the right choice here.  In practice,
I'd imagine these opportunities would only come from a DImode move of
$0 into a doubleword register, so we could simply emit the pattern in
mips_split_doubleword_move.

That would also allow us to use it for plain HI and LO.  It wasn't
obvious from the patch why it was restricted to the DSP extension
registers.

Please also add a scan-assembler test.

Richard
diff mbox

Patch

Index: gcc/config/mips/mips-dspr2.md
===================================================================
--- gcc/config/mips/mips-dspr2.md	(revision 190437)
+++ gcc/config/mips/mips-dspr2.md	(working copy)
@@ -68,6 +68,7 @@ 
   UNSPEC_DPAQX_SA_W_PH
   UNSPEC_DPSQX_S_W_PH
   UNSPEC_DPSQX_SA_W_PH
+  UNSPEC_ACC_INIT
 ])
 
 (define_insn "mips_absq_s_qb"
@@ -630,3 +631,33 @@ 
   [(set_attr "type"	"dspmacsat")
    (set_attr "accum_in" "1")
    (set_attr "mode"	"SI")])
+
+;; Convert  mtlo $ac[1-3],$0  =>  mult $ac[1-3],$0,$0
+;;          mthi $ac[1-3],$0
+(define_peephole2
+  [(set (match_operand:SI 0 "register_operand" "")
+	(const_int 0))
+   (set (match_operand:SI 1 "register_operand" "")
+	(const_int 0))]
+  "ISA_HAS_DSPR2
+   && !TARGET_MIPS16
+   && !TARGET_64BIT
+   && true_regnum (operands[0]) >= DSP_ACC_REG_FIRST
+   && true_regnum (operands[0]) <= DSP_ACC_REG_LAST
+   && true_regnum (operands[0]) / 2 == true_regnum (operands[1]) / 2"
+  [(parallel [(set (match_dup 0) (const_int 0))
+	      (set (match_dup 1) (const_int 0))
+	      (unspec [(const_int 0)] UNSPEC_ACC_INIT)])]
+)
+
+(define_insn "*mips_acc_init"
+  [(parallel
+    [(set (match_operand:SI 0 "register_operand" "=a") (const_int 0))
+     (set (match_operand:SI 1 "register_operand" "=a") (const_int 0))
+     (unspec [(const_int 0)] UNSPEC_ACC_INIT)])]
+  "ISA_HAS_DSPR2
+   && !TARGET_MIPS16
+   && !TARGET_64BIT"
+  "mult\t%q0,$0,$0\t\t# Clear ACC HI/LO"
+  [(set_attr "type"	"imul")
+   (set_attr "mode"	"SI")])