Patchwork [U-Boot,4/4,v3] xilinx: Add new Zynq board

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Submitter Michal Simek
Date Aug. 16, 2012, 6:30 a.m.
Message ID <1345098630-27902-4-git-send-email-monstr@monstr.eu>
Download mbox | patch
Permalink /patch/177909/
State Superseded
Delegated to: Albert ARIBAUD
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Comments

Michal Simek - Aug. 16, 2012, 6:30 a.m.
Add support for Xilinx Zynq board.

Signed-off-by: Michal Simek <monstr@monstr.eu>

---
v2: Forget to also add config file

v3: Change name for serial driver
    Remove lowlevel_init from board folder
    Remove XPSS part from timer baseaddr
    Change name for Zynq gem driver
    Clean coding style
    Remove mac + ip addresses from config file
    Remove additional PHYs
---
 board/xilinx/zynq/Makefile |   54 +++++++++++++++++++++
 board/xilinx/zynq/board.c  |   64 +++++++++++++++++++++++++
 boards.cfg                 |    1 +
 include/configs/zynq.h     |  110 ++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 229 insertions(+), 0 deletions(-)
 create mode 100644 board/xilinx/zynq/Makefile
 create mode 100644 board/xilinx/zynq/board.c
 create mode 100644 include/configs/zynq.h
Michal Simek - Sept. 12, 2012, 10:23 a.m.
On 08/16/2012 08:30 AM, Michal Simek wrote:
> Add support for Xilinx Zynq board.
>
> Signed-off-by: Michal Simek <monstr@monstr.eu>
>
> ---
> v2: Forget to also add config file
>
> v3: Change name for serial driver
>      Remove lowlevel_init from board folder
>      Remove XPSS part from timer baseaddr
>      Change name for Zynq gem driver
>      Clean coding style
>      Remove mac + ip addresses from config file
>      Remove additional PHYs
> ---
>   board/xilinx/zynq/Makefile |   54 +++++++++++++++++++++
>   board/xilinx/zynq/board.c  |   64 +++++++++++++++++++++++++
>   boards.cfg                 |    1 +
>   include/configs/zynq.h     |  110 ++++++++++++++++++++++++++++++++++++++++++++
>   4 files changed, 229 insertions(+), 0 deletions(-)
>   create mode 100644 board/xilinx/zynq/Makefile
>   create mode 100644 board/xilinx/zynq/board.c
>   create mode 100644 include/configs/zynq.h
>

The same for this one.
Marek and Joe: Can you please review this?

Thanks,
Michal
Marek Vasut - Sept. 13, 2012, 9:35 a.m.
Dear Michal Simek,

[...]

> +int board_init(void)
> +{
> +	icache_enable();

Uh oh ... isn't this on by default when CONFIG_ICACHE_OFF isn't present?

> +	return 0;
> +}
> +
> +int board_late_init(void)
> +{
> +	return 0;

You don't need this.

> +}
> +
> +#ifdef CONFIG_CMD_NET
> +int board_eth_init(bd_t *bis)
> +{
> +	int ret = 0;
> +
> +#if defined(CONFIG_ZYNQ_GEM) && defined(CONFIG_ZYNQ_GEM_BASEADDR0)
> +	ret |= zynq_gem_initialize(bis, CONFIG_ZYNQ_GEM_BASEADDR0);

ret |= ? ;-)

> +#endif
> +
> +	return ret;
> +}
> +#endif
> +
> +int dram_init(void)
> +{
> +	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
> +	return 0;
> +}
> +
> +void reset_cpu(ulong addr)
> +{
> +	while (1)
> +		;
> +}

This is definitelly CPU specific.
[...]
Michal Simek - Sept. 13, 2012, 9:55 a.m.
On 09/13/2012 11:35 AM, Marek Vasut wrote:
> Dear Michal Simek,
>
> [...]
>
>> +int board_init(void)
>> +{
>> +	icache_enable();
>
> Uh oh ... isn't this on by default when CONFIG_ICACHE_OFF isn't present?

Will check this one.

>
>> +	return 0;
>> +}
>> +
>> +int board_late_init(void)
>> +{
>> +	return 0;
>
> You don't need this.

Will check it too.

>
>> +}
>> +
>> +#ifdef CONFIG_CMD_NET
>> +int board_eth_init(bd_t *bis)
>> +{
>> +	int ret = 0;
>> +
>> +#if defined(CONFIG_ZYNQ_GEM) && defined(CONFIG_ZYNQ_GEM_BASEADDR0)
>> +	ret |= zynq_gem_initialize(bis, CONFIG_ZYNQ_GEM_BASEADDR0);
>
> ret |= ? ;-)

The reason is that I will wire axi_ethernet and ethernet lite drivers here too.
If this is the problem I can fix it but the next patch will return it
to this style.

>
>> +#endif
>> +
>> +	return ret;
>> +}
>> +#endif
>> +
>> +int dram_init(void)
>> +{
>> +	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
>> +	return 0;
>> +}
>> +
>> +void reset_cpu(ulong addr)
>> +{
>> +	while (1)
>> +		;
>> +}
>
> This is definitelly CPU specific.
> [...]
>
Right, Moving to different folder make sense.

Thanks,
Michal
Michal Simek - Sept. 13, 2012, 12:17 p.m.
On 09/13/2012 11:35 AM, Marek Vasut wrote:
> Dear Michal Simek,
>
> [...]
>
>> +int board_init(void)
>> +{
>> +	icache_enable();
>
> Uh oh ... isn't this on by default when CONFIG_ICACHE_OFF isn't present?

That option is valid just for blackfin.

In arm1176 and s3c44b0v is this done in arch_cpu_init()
but it is not there for armv7

I have seen that several armv7 boards enable it. For example vexpress, highbank, u8500, etc.

>
>> +	return 0;
>> +}
>> +
>> +int board_late_init(void)
>> +{
>> +	return 0;
>
> You don't need this.

correct.

Michal
Marek Vasut - Sept. 13, 2012, 12:31 p.m.
Dear Michal Simek,

> On 09/13/2012 11:35 AM, Marek Vasut wrote:
> > Dear Michal Simek,
> > 
> > [...]
> > 
> >> +int board_init(void)
> >> +{
> >> +	icache_enable();
> > 
> > Uh oh ... isn't this on by default when CONFIG_ICACHE_OFF isn't present?
> 
> Will check this one.
> 
> >> +	return 0;
> >> +}
> >> +
> >> +int board_late_init(void)
> >> +{
> >> +	return 0;
> > 
> > You don't need this.
> 
> Will check it too.
> 
> >> +}
> >> +
> >> +#ifdef CONFIG_CMD_NET
> >> +int board_eth_init(bd_t *bis)
> >> +{
> >> +	int ret = 0;
> >> +
> >> +#if defined(CONFIG_ZYNQ_GEM) && defined(CONFIG_ZYNQ_GEM_BASEADDR0)
> >> +	ret |= zynq_gem_initialize(bis, CONFIG_ZYNQ_GEM_BASEADDR0);
> > 
> > ret |= ? ;-)
> 
> The reason is that I will wire axi_ethernet and ethernet lite drivers here
> too. If this is the problem I can fix it but the next patch will return it
> to this style.

Logical OR on signed type is wrong. Besides, if one fails, you don't want to 
init the others.

> >> +#endif
> >> +
> >> +	return ret;
> >> +}
> >> +#endif
> >> +
> >> +int dram_init(void)
> >> +{
> >> +	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
> >> +	return 0;
> >> +}
> >> +
> >> +void reset_cpu(ulong addr)
> >> +{
> >> +	while (1)
> >> +		;
> >> +}
> > 
> > This is definitelly CPU specific.
> > [...]
> 
> Right, Moving to different folder make sense.

Directory, no wind blows here :p

> Thanks,
> Michal

Best regards,
Marek Vasut
Joe Hershberger - Sept. 14, 2012, 4:03 a.m.
Hi Michal,

On Thu, Aug 16, 2012 at 1:30 AM, Michal Simek <monstr@monstr.eu> wrote:
> Add support for Xilinx Zynq board.
>
> Signed-off-by: Michal Simek <monstr@monstr.eu>
>
> ---
> v2: Forget to also add config file
>
> v3: Change name for serial driver
>     Remove lowlevel_init from board folder
>     Remove XPSS part from timer baseaddr
>     Change name for Zynq gem driver
>     Clean coding style
>     Remove mac + ip addresses from config file
>     Remove additional PHYs
> ---
>  board/xilinx/zynq/Makefile |   54 +++++++++++++++++++++
>  board/xilinx/zynq/board.c  |   64 +++++++++++++++++++++++++
>  boards.cfg                 |    1 +
>  include/configs/zynq.h     |  110 ++++++++++++++++++++++++++++++++++++++++++++
>  4 files changed, 229 insertions(+), 0 deletions(-)
>  create mode 100644 board/xilinx/zynq/Makefile
>  create mode 100644 board/xilinx/zynq/board.c
>  create mode 100644 include/configs/zynq.h
>
> diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
> new file mode 100644
> index 0000000..4cb36f6
> --- /dev/null
> +++ b/board/xilinx/zynq/board.c
> @@ -0,0 +1,64 @@
> +/*
> + * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <netdev.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int board_init(void)
> +{
> +       icache_enable();
> +
> +       return 0;
> +}
> +
> +int board_late_init(void)
> +{
> +       return 0;
> +}
> +
> +#ifdef CONFIG_CMD_NET
> +int board_eth_init(bd_t *bis)
> +{
> +       int ret = 0;
> +
> +#if defined(CONFIG_ZYNQ_GEM) && defined(CONFIG_ZYNQ_GEM_BASEADDR0)
> +       ret |= zynq_gem_initialize(bis, CONFIG_ZYNQ_GEM_BASEADDR0);
> +#endif
> +
> +       return ret;
> +}
> +#endif
> +
> +int dram_init(void)
> +{
> +       gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
> +
> +       return 0;
> +}
> +
> +void reset_cpu(ulong addr)
> +{
> +       while (1)
> +               ;
> +}

Why not explicitly reset, like Xilinx tree?

void reset_cpu(ulong addr)
{
        /* unlock SLCR */
        writel(XPSS_SLCR_UNLOCK_KEY, XPSS_SYS_CTRL_BASEADDR | XPSS_SLCR_UNLOCK);
        /* Tickle soft reset bit */
        writel(1, XPSS_SYS_CTRL_BASEADDR | XPSS_SLCR_PSS_RST_CTRL);

        while (1)
                ;
}


> diff --git a/include/configs/zynq.h b/include/configs/zynq.h
> new file mode 100644
> index 0000000..8fb4f1b
> --- /dev/null
> +++ b/include/configs/zynq.h
> @@ -0,0 +1,110 @@
> +/*
> + * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __CONFIG_ZYNQ_H
> +#define __CONFIG_ZYNQ_H
> +
> +#define CONFIG_ARMV7 /* This is an ARM V7 CPU core */
> +#define CONFIG_ZYNQ
> +
> +/* CPU clock */
> +#define CONFIG_CPU_FREQ_HZ     800000000
> +#define CONFIG_SYS_HZ          1000
> +
> +/* Ram */
> +#define CONFIG_NR_DRAM_BANKS           1
> +#define CONFIG_SYS_SDRAM_BASE          0
> +#define CONFIG_SYS_SDRAM_SIZE          0x40000000
> +#define CONFIG_SYS_MEMTEST_START       CONFIG_SYS_SDRAM_BASE
> +#define CONFIG_SYS_MEMTEST_END         (CONFIG_SYS_SDRAM_BASE + 0x1000)
> +
> +/* The following table includes the supported baudrates */
> +#define CONFIG_SYS_BAUDRATE_TABLE  \
> +       {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
> +
> +#define CONFIG_BAUDRATE                115200
> +
> +/* XPSS Serial driver */
> +#define CONFIG_ZYNQ_SERIAL
> +#define CONFIG_ZYNQ_SERIAL_BASEADDR0   0xE0001000
> +#define CONFIG_ZYNQ_SERIAL_BAUDRATE0   CONFIG_BAUDRATE
> +#define CONFIG_ZYNQ_SERIAL_CLOCK0      50000000
> +
> +/* SCU timer address is hardcoded */
> +#define CONFIG_SCUTIMER_BASEADDR       0xF8F00600
> +
> +/* Ethernet driver */
> +#define CONFIG_NET_MULTI
> +#define CONFIG_ZYNQ_GEM
> +#define CONFIG_ZYNQ_GEM_BASEADDR0      0xE000B000
> +
> +#define CONFIG_BOOTP_SERVERIP
> +#define CONFIG_BOOTP_BOOTPATH
> +#define CONFIG_BOOTP_GATEWAY
> +#define CONFIG_BOOTP_HOSTNAME
> +#define CONFIG_BOOTP_MAY_FAIL
> +
> +/* MII and Phylib */
> +#define CONFIG_MII
> +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
> +#define CONFIG_PHYLIB
> +#define CONFIG_PHY_MARVELL
> +
> +/* Environment */
> +#define CONFIG_ENV_IS_NOWHERE
> +#define CONFIG_ENV_SIZE 0x10000
> +
> +#define CONFIG_SYS_NO_FLASH
> +
> +#define CONFIG_SYS_MALLOC_LEN          0x400000
> +#define CONFIG_SYS_INIT_RAM_ADDR       CONFIG_SYS_SDRAM_BASE
> +#define CONFIG_SYS_INIT_RAM_SIZE       CONFIG_SYS_MALLOC_LEN
> +#define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_INIT_RAM_ADDR + \
> +                                               CONFIG_SYS_INIT_RAM_SIZE - \
> +                                               GENERATED_GBL_DATA_SIZE)
> +
> +#define CONFIG_SYS_PROMPT      "U-Boot> "
> +#define CONFIG_SYS_CBSIZE      256 /* Console I/O Buffer Size */
> +#define CONFIG_SYS_PBSIZE      (CONFIG_SYS_CBSIZE + \
> +                                       sizeof(CONFIG_SYS_PROMPT) + 16)
> +
> +#define CONFIG_SYS_LOAD_ADDR   0
> +#define CONFIG_SYS_MAXARGS     15 /* max number of command args */
> +#define CONFIG_SYS_LONGHELP
> +#define CONFIG_AUTO_COMPLETE
> +#define CONFIG_CMDLINE_EDITING
> +
> +#define CONFIG_SYS_HUSH_PARSER
> +#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
> +
> +/* OF */
> +#define CONFIG_FIT
> +#define CONFIG_OF_LIBFDT
> +
> +/* Commands */
> +#include <config_cmd_default.h>
> +
> +#define CONFIG_CMD_PING
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_MII
> +
> +#endif /* __CONFIG_ZYNQ_H */
> --
> 1.7.0.4
>
Michal Simek - Sept. 14, 2012, 5:42 a.m.
On 09/14/2012 06:03 AM, Joe Hershberger wrote:
> Hi Michal,
>
> On Thu, Aug 16, 2012 at 1:30 AM, Michal Simek <monstr@monstr.eu> wrote:
>> Add support for Xilinx Zynq board.
>>
>> Signed-off-by: Michal Simek <monstr@monstr.eu>
>>
>> ---
>> v2: Forget to also add config file
>>
>> v3: Change name for serial driver
>>      Remove lowlevel_init from board folder
>>      Remove XPSS part from timer baseaddr
>>      Change name for Zynq gem driver
>>      Clean coding style
>>      Remove mac + ip addresses from config file
>>      Remove additional PHYs
>> ---
>>   board/xilinx/zynq/Makefile |   54 +++++++++++++++++++++
>>   board/xilinx/zynq/board.c  |   64 +++++++++++++++++++++++++
>>   boards.cfg                 |    1 +
>>   include/configs/zynq.h     |  110 ++++++++++++++++++++++++++++++++++++++++++++
>>   4 files changed, 229 insertions(+), 0 deletions(-)
>>   create mode 100644 board/xilinx/zynq/Makefile
>>   create mode 100644 board/xilinx/zynq/board.c
>>   create mode 100644 include/configs/zynq.h
>>
>> diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
>> new file mode 100644
>> index 0000000..4cb36f6
>> --- /dev/null
>> +++ b/board/xilinx/zynq/board.c
>> @@ -0,0 +1,64 @@
>> +/*
>> + * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
>> + *
>> + * See file CREDITS for list of people who contributed to this
>> + * project.
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of
>> + * the License, or (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>> + * MA 02111-1307 USA
>> + */
>> +
>> +#include <common.h>
>> +#include <netdev.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +int board_init(void)
>> +{
>> +       icache_enable();
>> +
>> +       return 0;
>> +}
>> +
>> +int board_late_init(void)
>> +{
>> +       return 0;
>> +}
>> +
>> +#ifdef CONFIG_CMD_NET
>> +int board_eth_init(bd_t *bis)
>> +{
>> +       int ret = 0;
>> +
>> +#if defined(CONFIG_ZYNQ_GEM) && defined(CONFIG_ZYNQ_GEM_BASEADDR0)
>> +       ret |= zynq_gem_initialize(bis, CONFIG_ZYNQ_GEM_BASEADDR0);
>> +#endif
>> +
>> +       return ret;
>> +}
>> +#endif
>> +
>> +int dram_init(void)
>> +{
>> +       gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
>> +
>> +       return 0;
>> +}
>> +
>> +void reset_cpu(ulong addr)
>> +{
>> +       while (1)
>> +               ;
>> +}
>
> Why not explicitly reset, like Xilinx tree?
>
> void reset_cpu(ulong addr)
> {
>          /* unlock SLCR */
>          writel(XPSS_SLCR_UNLOCK_KEY, XPSS_SYS_CTRL_BASEADDR | XPSS_SLCR_UNLOCK);
>          /* Tickle soft reset bit */
>          writel(1, XPSS_SYS_CTRL_BASEADDR | XPSS_SLCR_PSS_RST_CTRL);
>
>          while (1)
>                  ;
> }
>

I haven't started to merge all these features and want to merge minimum platform
and then start to clean drivers and features.
Maybe for slcr make sense to create driver and not just unlock it and use
it for code.

Thanks,
Michal

Patch

diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile
new file mode 100644
index 0000000..ef4faa1
--- /dev/null
+++ b/board/xilinx/zynq/Makefile
@@ -0,0 +1,54 @@ 
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= board.o
+
+COBJS	:= $(sort $(COBJS-y))
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
new file mode 100644
index 0000000..4cb36f6
--- /dev/null
+++ b/board/xilinx/zynq/board.c
@@ -0,0 +1,64 @@ 
+/*
+ * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	icache_enable();
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int ret = 0;
+
+#if defined(CONFIG_ZYNQ_GEM) && defined(CONFIG_ZYNQ_GEM_BASEADDR0)
+	ret |= zynq_gem_initialize(bis, CONFIG_ZYNQ_GEM_BASEADDR0);
+#endif
+
+	return ret;
+}
+#endif
+
+int dram_init(void)
+{
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+	while (1)
+		;
+}
diff --git a/boards.cfg b/boards.cfg
index fdb84ad..aeca912 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -261,6 +261,7 @@  seaboard                     arm         armv7       seaboard            nvidia
 ventana                      arm         armv7       ventana             nvidia         tegra2
 whistler                     arm         armv7       whistler            nvidia         tegra2
 u8500_href                   arm         armv7       u8500               st-ericsson    u8500
+zynq                         arm         armv7       zynq                xilinx         zynq
 actux1_4_16                  arm         ixp         actux1              -              -           actux1:FLASH2X2
 actux1_4_32                  arm         ixp         actux1              -              -           actux1:FLASH2X2,RAM_32MB
 actux1_8_16                  arm         ixp         actux1              -              -           actux1:FLASH1X8
diff --git a/include/configs/zynq.h b/include/configs/zynq.h
new file mode 100644
index 0000000..8fb4f1b
--- /dev/null
+++ b/include/configs/zynq.h
@@ -0,0 +1,110 @@ 
+/*
+ * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_ZYNQ_H
+#define __CONFIG_ZYNQ_H
+
+#define CONFIG_ARMV7 /* This is an ARM V7 CPU core */
+#define CONFIG_ZYNQ
+
+/* CPU clock */
+#define CONFIG_CPU_FREQ_HZ	800000000
+#define CONFIG_SYS_HZ		1000
+
+/* Ram */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		0
+#define CONFIG_SYS_SDRAM_SIZE		0x40000000
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x1000)
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+#define CONFIG_BAUDRATE		115200
+
+/* XPSS Serial driver */
+#define CONFIG_ZYNQ_SERIAL
+#define CONFIG_ZYNQ_SERIAL_BASEADDR0	0xE0001000
+#define CONFIG_ZYNQ_SERIAL_BAUDRATE0	CONFIG_BAUDRATE
+#define CONFIG_ZYNQ_SERIAL_CLOCK0	50000000
+
+/* SCU timer address is hardcoded */
+#define CONFIG_SCUTIMER_BASEADDR	0xF8F00600
+
+/* Ethernet driver */
+#define CONFIG_NET_MULTI
+#define CONFIG_ZYNQ_GEM
+#define CONFIG_ZYNQ_GEM_BASEADDR0	0xE000B000
+
+#define CONFIG_BOOTP_SERVERIP
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_MAY_FAIL
+
+/* MII and Phylib */
+#define CONFIG_MII
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MARVELL
+
+/* Environment */
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE 0x10000
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SYS_MALLOC_LEN		0x400000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+						CONFIG_SYS_INIT_RAM_SIZE - \
+						GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_PROMPT	"U-Boot> "
+#define CONFIG_SYS_CBSIZE	256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_SYS_LOAD_ADDR	0
+#define CONFIG_SYS_MAXARGS	15 /* max number of command args */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+
+/* OF */
+#define CONFIG_FIT
+#define CONFIG_OF_LIBFDT
+
+/* Commands */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+
+#endif /* __CONFIG_ZYNQ_H */