From patchwork Thu Aug 16 03:58:22 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar Kushwaha X-Patchwork-Id: 177893 X-Patchwork-Delegate: galak@kernel.crashing.org Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id 78CA92C0149 for ; Thu, 16 Aug 2012 13:59:13 +1000 (EST) Received: from co1outboundpool.messaging.microsoft.com (co1ehsobe003.messaging.microsoft.com [216.32.180.186]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (Client CN "mail.global.frontbridge.com", Issuer "Microsoft Secure Server Authority" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 637DD2C008F for ; Thu, 16 Aug 2012 13:58:48 +1000 (EST) Received: from mail205-co1-R.bigfish.com (10.243.78.240) by CO1EHSOBE006.bigfish.com (10.243.66.69) with Microsoft SMTP Server id 14.1.225.23; Thu, 16 Aug 2012 03:58:43 +0000 Received: from mail205-co1 (localhost [127.0.0.1]) by mail205-co1-R.bigfish.com (Postfix) with ESMTP id C10DD760108; Thu, 16 Aug 2012 03:58:42 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275bh8275dhz2dh2a8h668h839hd24he5bhf0ah107ah) Received: from mail205-co1 (localhost.localdomain [127.0.0.1]) by mail205-co1 (MessageSwitch) id 1345089519177808_20311; Thu, 16 Aug 2012 03:58:39 +0000 (UTC) Received: from CO1EHSMHS027.bigfish.com (unknown [10.243.78.225]) by mail205-co1.bigfish.com (Postfix) with ESMTP id 295099A005B; Thu, 16 Aug 2012 03:58:39 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CO1EHSMHS027.bigfish.com (10.243.66.37) with Microsoft SMTP Server (TLS) id 14.1.225.23; Thu, 16 Aug 2012 03:58:39 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server (TLS) id 14.2.298.5; Wed, 15 Aug 2012 22:58:37 -0500 Received: from b32579-VirtualBox.ap.freescale.net (B32579-02.ap.freescale.net [10.232.132.181]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id q7G3wSRm002877; Wed, 15 Aug 2012 20:58:34 -0700 From: Prabhakar Kushwaha To: Subject: [PATCH] powerpc/mpc85xx:Add new ext fields to Integrated FLash Controller Date: Thu, 16 Aug 2012 09:28:22 +0530 Message-ID: <1345089502-23979-1-git-send-email-prabhakar@freescale.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-OriginatorOrg: freescale.com Cc: Prabhakar Kushwaha , York Sun X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Freescale's Integrated Flash controller(IFC) v1.1.0 supports 40 bit address bus width. In case more than 32 bit address is used, the EXT registers should be set. Add support of ext registers. Signed-off-by: Kumar Gala Signed-off-by: York Sun Signed-off-by: Prabhakar Kushwaha --- Base upon git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git Branch next arch/powerpc/include/asm/fsl_ifc.h | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/arch/powerpc/include/asm/fsl_ifc.h index b955012..b8a4b9b 100644 --- a/arch/powerpc/include/asm/fsl_ifc.h +++ b/arch/powerpc/include/asm/fsl_ifc.h @@ -768,22 +768,24 @@ struct fsl_ifc_gpcm { */ struct fsl_ifc_regs { __be32 ifc_rev; - u32 res1[0x3]; + u32 res1[0x2]; struct { + __be32 cspr_ext; __be32 cspr; - u32 res2[0x2]; + u32 res2; } cspr_cs[FSL_IFC_BANK_COUNT]; - u32 res3[0x18]; + u32 res3[0x19]; struct { __be32 amask; u32 res4[0x2]; } amask_cs[FSL_IFC_BANK_COUNT]; - u32 res5[0x18]; + u32 res5[0x17]; struct { + __be32 csor_ext; __be32 csor; - u32 res6[0x2]; + u32 res6; } csor_cs[FSL_IFC_BANK_COUNT]; - u32 res7[0x18]; + u32 res7[0x19]; struct { __be32 ftim[4]; u32 res8[0x8];