Patchwork powerpc/mpc85xx:Add new ext fields to Integrated FLash Controller

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Submitter Prabhakar Kushwaha
Date Aug. 16, 2012, 3:58 a.m.
Message ID <1345089502-23979-1-git-send-email-prabhakar@freescale.com>
Download mbox | patch
Permalink /patch/177893/
State Accepted
Commit 0adbe663bdf9d80a9ab1d225a5cc030fe2be10b5
Delegated to: Kumar Gala
Headers show

Comments

Prabhakar Kushwaha - Aug. 16, 2012, 3:58 a.m.
Freescale's Integrated Flash controller(IFC) v1.1.0 supports 40 bit
address bus width. 
In case more than 32 bit address is used, the EXT registers should be set.

Add support of ext registers.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
Base upon git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
Branch next

 arch/powerpc/include/asm/fsl_ifc.h |   14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)
Kumar Gala - Aug. 17, 2012, 2:07 p.m.
On Aug 15, 2012, at 10:58 PM, Prabhakar Kushwaha wrote:

> Freescale's Integrated Flash controller(IFC) v1.1.0 supports 40 bit
> address bus width. 
> In case more than 32 bit address is used, the EXT registers should be set.
> 
> Add support of ext registers.
> 
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> Signed-off-by: York Sun <yorksun@freescale.com>
> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> ---
> Base upon git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
> Branch next
> 
> arch/powerpc/include/asm/fsl_ifc.h |   14 ++++++++------
> 1 file changed, 8 insertions(+), 6 deletions(-)

applied to next

- k

Patch

diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/arch/powerpc/include/asm/fsl_ifc.h
index b955012..b8a4b9b 100644
--- a/arch/powerpc/include/asm/fsl_ifc.h
+++ b/arch/powerpc/include/asm/fsl_ifc.h
@@ -768,22 +768,24 @@  struct fsl_ifc_gpcm {
  */
 struct fsl_ifc_regs {
 	__be32 ifc_rev;
-	u32 res1[0x3];
+	u32 res1[0x2];
 	struct {
+		__be32 cspr_ext;
 		__be32 cspr;
-		u32 res2[0x2];
+		u32 res2;
 	} cspr_cs[FSL_IFC_BANK_COUNT];
-	u32 res3[0x18];
+	u32 res3[0x19];
 	struct {
 		__be32 amask;
 		u32 res4[0x2];
 	} amask_cs[FSL_IFC_BANK_COUNT];
-	u32 res5[0x18];
+	u32 res5[0x17];
 	struct {
+		__be32 csor_ext;
 		__be32 csor;
-		u32 res6[0x2];
+		u32 res6;
 	} csor_cs[FSL_IFC_BANK_COUNT];
-	u32 res7[0x18];
+	u32 res7[0x19];
 	struct {
 		__be32 ftim[4];
 		u32 res8[0x8];