Patchwork msr: remove the IA32_A_PMC0-3 and IA32_TSC_AUX from cosistent test

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Submitter Ivan Hu
Date Aug. 15, 2012, 8:41 a.m.
Message ID <1345020095-22182-1-git-send-email-ivan.hu@canonical.com>
Download mbox | patch
Permalink /patch/177573/
State Accepted
Headers show

Comments

Ivan Hu - Aug. 15, 2012, 8:41 a.m.
checking from Intel 64 and IA32 software architectures develope manual,
the Scope of these MSRs is Thread, it means this bit field must be
programmed on each logical processor independently.

Signed-off-by: Ivan Hu <ivan.hu@canonical.com>
---
 src/cpu/msr/msr.c |    5 -----
 1 file changed, 5 deletions(-)
Colin King - Aug. 17, 2012, 12:38 p.m.
On 15/08/12 09:41, Ivan Hu wrote:
> checking from Intel 64 and IA32 software architectures develope manual,
> the Scope of these MSRs is Thread, it means this bit field must be
> programmed on each logical processor independently.
>
> Signed-off-by: Ivan Hu <ivan.hu@canonical.com>
> ---
>   src/cpu/msr/msr.c |    5 -----
>   1 file changed, 5 deletions(-)
>
> diff --git a/src/cpu/msr/msr.c b/src/cpu/msr/msr.c
> index 5de27a7..0a8cf2c 100644
> --- a/src/cpu/msr/msr.c
> +++ b/src/cpu/msr/msr.c
> @@ -423,10 +423,6 @@ static msr_info IA32_MSRs[] = {
>   	{ "VMX_TRUE_EXIT_CTLS",	0x0000048f,	0, ~0, NULL },
>   	{ "VMX_TRUE_ENTRY_CTLS",0x00000490,	0, ~0, NULL },
>
> -	{ "A_PMC0",		0x000004c1,	0, ~0, NULL },
> -	{ "A_PMC1",		0x000004c2,	0, ~0, NULL },
> -	{ "A_PMC2",		0x000004c3,	0, ~0, NULL },
> -	{ "A_PMC3",		0x000004c4,	0, ~0, NULL },
>   	{ "A_PMC4",		0x000004c5,	0, ~0, NULL },
>   	{ "A_PMC5",		0x000004c6,	0, ~0, NULL },
>   	{ "A_PMC6",		0x000004c7,	0, ~0, NULL },
> @@ -439,7 +435,6 @@ static msr_info IA32_MSRs[] = {
>   	//{ "FS_BASE",		0xc0000100,	0, ~0, NULL },
>   	//{ "GS_BASE",		0xc0000101, 	0, ~0, NULL },
>   	{ "KERNEL_GS_BASE",	0xc0000102, 	0, ~0, NULL },
> -	{ "TSC_AUX",		0xc0000103, 	0, 0xffffffffULL, NULL },
>   	{ NULL,			0x00000000,	0, 0 , NULL },
>   };
>
>
Makes a load of sense.

Acked-by: Colin Ian King <colin.king@canonical.com>
Alex Hung - Aug. 18, 2012, 11:58 a.m.
On 08/17/2012 08:38 PM, Colin Ian King wrote:
> On 15/08/12 09:41, Ivan Hu wrote:
>> checking from Intel 64 and IA32 software architectures develope manual,
>> the Scope of these MSRs is Thread, it means this bit field must be
>> programmed on each logical processor independently.
>>
>> Signed-off-by: Ivan Hu <ivan.hu@canonical.com>
>> ---
>>   src/cpu/msr/msr.c |    5 -----
>>   1 file changed, 5 deletions(-)
>>
>> diff --git a/src/cpu/msr/msr.c b/src/cpu/msr/msr.c
>> index 5de27a7..0a8cf2c 100644
>> --- a/src/cpu/msr/msr.c
>> +++ b/src/cpu/msr/msr.c
>> @@ -423,10 +423,6 @@ static msr_info IA32_MSRs[] = {
>>       { "VMX_TRUE_EXIT_CTLS",    0x0000048f,    0, ~0, NULL },
>>       { "VMX_TRUE_ENTRY_CTLS",0x00000490,    0, ~0, NULL },
>>
>> -    { "A_PMC0",        0x000004c1,    0, ~0, NULL },
>> -    { "A_PMC1",        0x000004c2,    0, ~0, NULL },
>> -    { "A_PMC2",        0x000004c3,    0, ~0, NULL },
>> -    { "A_PMC3",        0x000004c4,    0, ~0, NULL },
>>       { "A_PMC4",        0x000004c5,    0, ~0, NULL },
>>       { "A_PMC5",        0x000004c6,    0, ~0, NULL },
>>       { "A_PMC6",        0x000004c7,    0, ~0, NULL },
>> @@ -439,7 +435,6 @@ static msr_info IA32_MSRs[] = {
>>       //{ "FS_BASE",        0xc0000100,    0, ~0, NULL },
>>       //{ "GS_BASE",        0xc0000101,     0, ~0, NULL },
>>       { "KERNEL_GS_BASE",    0xc0000102,     0, ~0, NULL },
>> -    { "TSC_AUX",        0xc0000103,     0, 0xffffffffULL, NULL },
>>       { NULL,            0x00000000,    0, 0 , NULL },
>>   };
>>
>>
> Makes a load of sense.
>
> Acked-by: Colin Ian King <colin.king@canonical.com>
>
Acked-by: Alex Hung <alex.hung@canonical.com>

Patch

diff --git a/src/cpu/msr/msr.c b/src/cpu/msr/msr.c
index 5de27a7..0a8cf2c 100644
--- a/src/cpu/msr/msr.c
+++ b/src/cpu/msr/msr.c
@@ -423,10 +423,6 @@  static msr_info IA32_MSRs[] = {
 	{ "VMX_TRUE_EXIT_CTLS",	0x0000048f,	0, ~0, NULL },
 	{ "VMX_TRUE_ENTRY_CTLS",0x00000490,	0, ~0, NULL },
 
-	{ "A_PMC0",		0x000004c1,	0, ~0, NULL },
-	{ "A_PMC1",		0x000004c2,	0, ~0, NULL },
-	{ "A_PMC2",		0x000004c3,	0, ~0, NULL },
-	{ "A_PMC3",		0x000004c4,	0, ~0, NULL },
 	{ "A_PMC4",		0x000004c5,	0, ~0, NULL },
 	{ "A_PMC5",		0x000004c6,	0, ~0, NULL },
 	{ "A_PMC6",		0x000004c7,	0, ~0, NULL },
@@ -439,7 +435,6 @@  static msr_info IA32_MSRs[] = {
 	//{ "FS_BASE",		0xc0000100,	0, ~0, NULL },
 	//{ "GS_BASE",		0xc0000101, 	0, ~0, NULL },
 	{ "KERNEL_GS_BASE",	0xc0000102, 	0, ~0, NULL },
-	{ "TSC_AUX",		0xc0000103, 	0, 0xffffffffULL, NULL },
 	{ NULL,			0x00000000,	0, 0 , NULL },
 };