From patchwork Tue Aug 14 19:53:15 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Beno=C3=AEt_Th=C3=A9baudeau?= X-Patchwork-Id: 177429 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id AEFD62C008B for ; Wed, 15 Aug 2012 05:48:03 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EA46428097; Tue, 14 Aug 2012 21:48:01 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id bxaqNWlTbb1H; Tue, 14 Aug 2012 21:48:01 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BC761280A6; Tue, 14 Aug 2012 21:47:58 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C0EAD280A6 for ; Tue, 14 Aug 2012 21:47:57 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id DtT+4sIRmRto for ; Tue, 14 Aug 2012 21:47:57 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from zose-mta15.web4all.fr (zose-mta15.web4all.fr [176.31.217.11]) by theia.denx.de (Postfix) with ESMTP id 134F228097 for ; Tue, 14 Aug 2012 21:47:55 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by zose-mta15.web4all.fr (Postfix) with ESMTP id 64DF12D2C7; Tue, 14 Aug 2012 21:50:36 +0200 (CEST) X-Virus-Scanned: amavisd-new at zose1.web4all.fr Received: from zose-mta15.web4all.fr ([127.0.0.1]) by localhost (zose-mta15.web4all.fr [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id z3RttGxtTSDb; Tue, 14 Aug 2012 21:50:35 +0200 (CEST) Received: from zose-store12.web4all.fr (zose-store-12.w4a.fr [178.33.204.48]) by zose-mta15.web4all.fr (Postfix) with ESMTP id CCEE02C373; Tue, 14 Aug 2012 21:50:35 +0200 (CEST) Date: Tue, 14 Aug 2012 21:53:15 +0200 (CEST) From: =?utf-8?Q?Beno=C3=AEt_Th=C3=A9baudeau?= To: U-Boot-Users ML Message-ID: <662576707.2410929.1344973995206.JavaMail.root@advansee.com> MIME-Version: 1.0 X-Originating-IP: [88.188.188.98] X-Mailer: Zimbra 7.2.0_GA_2669 (ZimbraWebClient - FF3.0 (Win)/7.2.0_GA_2669) Subject: [U-Boot] [PATCH] mx35 timer: Switch to 32-kHz source X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Switch the mx35 timer driver to the 32-kHz clock source to avoid calling mxc_get_clock() again and again, and to be consistent with the timer drivers of other i.MX SoCs. Signed-off-by: Benoît Thébaudeau Cc: Stefano Babic --- .../arch/arm/cpu/arm1136/mx35/timer.c | 43 ++++++++++++-------- .../include/configs/flea3.h | 1 + .../include/configs/mx35pdk.h | 1 + 3 files changed, 27 insertions(+), 18 deletions(-) diff --git u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/timer.c u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/timer.c index 04937a1..25057af 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/timer.c +++ u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/timer.c @@ -27,7 +27,7 @@ #include #include #include -#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -37,43 +37,50 @@ DECLARE_GLOBAL_DATA_PTR; /* General purpose timers bitfields */ #define GPTCR_SWR (1<<15) /* Software reset */ #define GPTCR_FRR (1<<9) /* Freerun / restart */ -#define GPTCR_CLKSOURCE_32 (0x100<<6) /* Clock source */ -#define GPTCR_CLKSOURCE_IPG (0x001<<6) /* Clock source */ +#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */ #define GPTCR_TEN (1) /* Timer enable */ -#define TIMER_FREQ_HZ mxc_get_clock(MXC_IPG_CLK) - +/* + * "time" is measured in 1 / CONFIG_SYS_HZ seconds, + * "tick" is internal timer period + */ +/* ~0.4% error - measured with stop-watch on 100s boot-delay */ static inline unsigned long long tick_to_time(unsigned long long tick) { tick *= CONFIG_SYS_HZ; - do_div(tick, TIMER_FREQ_HZ); + do_div(tick, CONFIG_MX35_CLK32); return tick; } -static inline unsigned long long us_to_tick(unsigned long long usec) +static inline unsigned long long us_to_tick(unsigned long long us) { - usec *= TIMER_FREQ_HZ; - do_div(usec, 1000000); + us = us * CONFIG_MX35_CLK32 + 999999; + do_div(us, 1000000); - return usec; + return us; } +/* nothing really to do with interrupts, just starts up a counter. */ +/* The 32KHz 32-bit timer overruns in 134217 seconds */ int timer_init(void) { int i; struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR; + struct ccm_regs *ccm = (struct ccm_regs *)CCM_BASE_ADDR; /* setup GP Timer 1 */ writel(GPTCR_SWR, &gpt->ctrl); - for (i = 0; i < 100; i++) - writel(0, &gpt->ctrl); /* We have no udelay by now */ - writel(0, &gpt->pre); - /* Freerun Mode, PERCLK1 input */ - writel(readl(&gpt->ctrl) | - GPTCR_CLKSOURCE_IPG | GPTCR_TEN, - &gpt->ctrl); + writel(readl(&ccm->cgr1) | 3 << MXC_CCM_CGR1_GPT_OFFSET, &ccm->cgr1); + + for (i = 0; i < 100; i++) + writel(0, &gpt->ctrl); /* We have no udelay by now */ + writel(0, &gpt->pre); /* prescaler = 1 */ + /* Freerun Mode, 32KHz input */ + writel(readl(&gpt->ctrl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, + &gpt->ctrl); + writel(readl(&gpt->ctrl) | GPTCR_TEN, &gpt->ctrl); return 0; } @@ -132,5 +139,5 @@ void __udelay(unsigned long usec) */ ulong get_tbclk(void) { - return TIMER_FREQ_HZ; + return CONFIG_MX35_CLK32; } diff --git u-boot-4d3c95f.orig/include/configs/flea3.h u-boot-4d3c95f/include/configs/flea3.h index 46939d4..26f1b3e 100644 --- u-boot-4d3c95f.orig/include/configs/flea3.h +++ u-boot-4d3c95f/include/configs/flea3.h @@ -32,6 +32,7 @@ #define CONFIG_ARM1136 /* This is an arm1136 CPU core */ #define CONFIG_MX35 #define CONFIG_MX35_HCLK_FREQ 24000000 +#define CONFIG_MX35_CLK32 32768 #define CONFIG_SYS_DCACHE_OFF #define CONFIG_SYS_CACHELINE_SIZE 32 diff --git u-boot-4d3c95f.orig/include/configs/mx35pdk.h u-boot-4d3c95f/include/configs/mx35pdk.h index 6eb5da5..d66f16b 100644 --- u-boot-4d3c95f.orig/include/configs/mx35pdk.h +++ u-boot-4d3c95f/include/configs/mx35pdk.h @@ -32,6 +32,7 @@ #define CONFIG_ARM1136 /* This is an arm1136 CPU core */ #define CONFIG_MX35 #define CONFIG_MX35_HCLK_FREQ 24000000 +#define CONFIG_MX35_CLK32 32768 #define CONFIG_DISPLAY_CPUINFO