From patchwork Tue Aug 14 18:43:07 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Beno=C3=AEt_Th=C3=A9baudeau?= X-Patchwork-Id: 177412 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id E2D012C0081 for ; Wed, 15 Aug 2012 04:37:55 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2BF3C28090; Tue, 14 Aug 2012 20:37:54 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id y9cdRYfd1G5u; Tue, 14 Aug 2012 20:37:53 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5FF8F2808A; Tue, 14 Aug 2012 20:37:52 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0CAE22808A for ; Tue, 14 Aug 2012 20:37:51 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id GZS4I5ba7paP for ; Tue, 14 Aug 2012 20:37:49 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from zose-mta11.web4all.fr (zose-mta-11.w4a.fr [178.33.204.86]) by theia.denx.de (Postfix) with ESMTP id D0C7E28088 for ; Tue, 14 Aug 2012 20:37:48 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by zose-mta11.web4all.fr (Postfix) with ESMTP id 5F23D46015; Tue, 14 Aug 2012 20:42:34 +0200 (CEST) X-Virus-Scanned: amavisd-new at zose1.web4all.fr Received: from zose-mta11.web4all.fr ([127.0.0.1]) by localhost (zose-mta11.web4all.fr [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Jo63r5leHlFy; Tue, 14 Aug 2012 20:42:33 +0200 (CEST) Received: from zose-store12.web4all.fr (zose-store12.web4all.fr [178.33.204.49]) by zose-mta11.web4all.fr (Postfix) with ESMTP id 9525046012; Tue, 14 Aug 2012 20:42:33 +0200 (CEST) Date: Tue, 14 Aug 2012 20:43:07 +0200 (CEST) From: =?utf-8?Q?Beno=C3=AEt_Th=C3=A9baudeau?= To: U-Boot-Users ML Message-ID: <1134893002.2409191.1344969787626.JavaMail.root@advansee.com> MIME-Version: 1.0 X-Originating-IP: [88.188.188.98] X-Mailer: Zimbra 7.2.0_GA_2669 (ZimbraWebClient - FF3.0 (Win)/7.2.0_GA_2669) Subject: [U-Boot] [PATCH] mx31: Fix PDR0_CSI_PODF X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de The CSI PODF bit-field used by the previous code for the i.MX31 CCM PDR0 register is actually composed of two bit-fields: one pre-divider and one post-divider. This patch fixes the CCM access macros and the code using them accordingly. Signed-off-by: Benoît Thébaudeau Cc: Stefano Babic --- .../arch/arm/include/asm/arch-mx31/imx-regs.h | 6 ++++-- .../board/freescale/mx31ads/lowlevel_init.S | 4 ++-- .../board/hale/tt01/tt01.c | 2 +- .../board/imx31_phycore/lowlevel_init.S | 2 +- .../board/logicpd/imx31_litekit/lowlevel_init.S | 2 +- .../include/configs/mx31pdk.h | 10 +++++----- 6 files changed, 14 insertions(+), 12 deletions(-) diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx31/imx-regs.h u-boot-4d3c95f/arch/arm/include/asm/arch-mx31/imx-regs.h index 7ddbbd6..6ec5fa7 100644 --- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx31/imx-regs.h +++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -567,7 +567,8 @@ struct esdc_regs { #define MX31_IIM_BASE_ADDR 0x5001C000 -#define PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23) +#define PDR0_CSI_PODF(x) (((x) & 0x3f) << 26) +#define PDR0_CSI_PRDF(x) (((x) & 0x7) << 23) #define PDR0_PER_PODF(x) (((x) & 0x1f) << 16) #define PDR0_HSP_PODF(x) (((x) & 0x7) << 11) #define PDR0_NFC_PODF(x) (((x) & 0x7) << 8) @@ -580,7 +581,8 @@ struct esdc_regs { #define PLL_MFI(x) (((x) & 0xf) << 10) #define PLL_MFN(x) (((x) & 0x3ff) << 0) -#define GET_PDR0_CSI_PODF(x) (((x) >> 23) & 0x1ff) +#define GET_PDR0_CSI_PODF(x) (((x) >> 26) & 0x3f) +#define GET_PDR0_CSI_PRDF(x) (((x) >> 23) & 0x7) #define GET_PDR0_PER_PODF(x) (((x) >> 16) & 0x1f) #define GET_PDR0_HSP_PODF(x) (((x) >> 11) & 0x7) #define GET_PDR0_NFC_PODF(x) (((x) >> 8) & 0x7) diff --git u-boot-4d3c95f.orig/board/freescale/mx31ads/lowlevel_init.S u-boot-4d3c95f/board/freescale/mx31ads/lowlevel_init.S index 5c18bc1..2972065 100644 --- u-boot-4d3c95f.orig/board/freescale/mx31ads/lowlevel_init.S +++ u-boot-4d3c95f/board/freescale/mx31ads/lowlevel_init.S @@ -246,8 +246,8 @@ lowlevel_init: /* COSR */ str r1, [r0, #0x1c] - /* RedBoot sets 0x1ff, 7, 3, 5, 1, 3, 0 */ -/* REG CCM_PDR0, PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)*/ + /* RedBoot sets 0x3f, 7, 7, 3, 5, 1, 3, 0 */ +/* REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)*/ /* Redboot: 0, 51, 10, 12 / 0, 14, 9, 13 */ /* REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)*/ diff --git u-boot-4d3c95f.orig/board/hale/tt01/tt01.c u-boot-4d3c95f/board/hale/tt01/tt01.c index 02e75ed..143fcef 100644 --- u-boot-4d3c95f.orig/board/hale/tt01/tt01.c +++ u-boot-4d3c95f/board/hale/tt01/tt01.c @@ -52,7 +52,7 @@ static void board_setup_clocks(void) writel((CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS, &ccm->ccmr); /* Set up clock to 532MHz */ - writel(PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | + writel(PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0), &ccm->pdr0); diff --git u-boot-4d3c95f.orig/board/imx31_phycore/lowlevel_init.S u-boot-4d3c95f/board/imx31_phycore/lowlevel_init.S index c47137d..4dd78b6 100644 --- u-boot-4d3c95f.orig/board/imx31_phycore/lowlevel_init.S +++ u-boot-4d3c95f/board/imx31_phycore/lowlevel_init.S @@ -54,7 +54,7 @@ lowlevel_init: REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS - REG CCM_PDR0, PDR0_CSI_PODF(0xff1) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0) + REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0) REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0xe) | PLL_MFI(9) | PLL_MFN(0xd) diff --git u-boot-4d3c95f.orig/board/logicpd/imx31_litekit/lowlevel_init.S u-boot-4d3c95f/board/logicpd/imx31_litekit/lowlevel_init.S index 95b0c08..0ce8905 100644 --- u-boot-4d3c95f.orig/board/logicpd/imx31_litekit/lowlevel_init.S +++ u-boot-4d3c95f/board/logicpd/imx31_litekit/lowlevel_init.S @@ -54,7 +54,7 @@ lowlevel_init: REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS - REG CCM_PDR0, PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0) + REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0) REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23) REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1) diff --git u-boot-4d3c95f.orig/include/configs/mx31pdk.h u-boot-4d3c95f/include/configs/mx31pdk.h index 7634de7..4900be0 100644 --- u-boot-4d3c95f.orig/include/configs/mx31pdk.h +++ u-boot-4d3c95f/include/configs/mx31pdk.h @@ -212,11 +212,11 @@ /* Configuration of lowlevel_init.S (clocks and SDRAM) */ #define CCM_CCMR_SETUP 0x074B0BF5 -#define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | \ - PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | \ - PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | \ - PDR0_MCU_PODF(0)) -#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \ +#define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \ + PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | \ + PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | \ + PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)) +#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \ PLL_MFN(12)) #define ESDMISC_MDDR_SETUP 0x00000004