diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/lowlevel_init.S
index d0f75fa..b25b3a7 100644
--- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/lowlevel_init.S
@@ -330,7 +330,7 @@ ENTRY(lowlevel_init)
 	mov r10, lr
 	mov r4, #0	/* Fix R4 to 0 */
 
-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SYS_MAIN_PWR_ON)
 	ldr r0, =GPIO1_BASE_ADDR
 	ldr r1, [r0, #0x0]
 	orr r1, r1, #1 << 23
diff --git u-boot-4d3c95f.orig/doc/README.imx5 u-boot-4d3c95f/doc/README.imx5
index 938d3da..85d476f 100644
--- u-boot-4d3c95f.orig/doc/README.imx5
+++ u-boot-4d3c95f/doc/README.imx5
@@ -20,3 +20,8 @@ i.MX5x SoCs.
     mode), which causes the effect of this failure to be much lower (in terms
     of frequency deviation), avoiding system failure, or at least decreasing
     the likelihood of system failure.
+
+1.3 CONFIG_SYS_MAIN_PWR_ON: Trigger MAIN_PWR_ON upon startup.
+    This option should be enabled for boards having a SYS_ON_OFF_CTL signal
+    connected to GPIO1[23] and triggering the MAIN_PWR_ON signal like in the
+    reference designs.
diff --git u-boot-4d3c95f.orig/include/configs/efikamx.h u-boot-4d3c95f/include/configs/efikamx.h
index 143b0f0..792b51b 100644
--- u-boot-4d3c95f.orig/include/configs/efikamx.h
+++ u-boot-4d3c95f/include/configs/efikamx.h
@@ -270,5 +270,6 @@
 
 #define CONFIG_SYS_DDR_CLKSEL		0
 #define CONFIG_SYS_CLKTL_CBCDR		0x59E35145
+#define CONFIG_SYS_MAIN_PWR_ON
 
 #endif
diff --git u-boot-4d3c95f.orig/include/configs/mx51evk.h u-boot-4d3c95f/include/configs/mx51evk.h
index e975f54..6867f7b 100644
--- u-boot-4d3c95f.orig/include/configs/mx51evk.h
+++ u-boot-4d3c95f/include/configs/mx51evk.h
@@ -242,6 +242,7 @@
 
 #define CONFIG_SYS_DDR_CLKSEL	0
 #define CONFIG_SYS_CLKTL_CBCDR	0x59E35100
+#define CONFIG_SYS_MAIN_PWR_ON
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
diff --git u-boot-4d3c95f.orig/include/configs/vision2.h u-boot-4d3c95f/include/configs/vision2.h
index ed004a6..3ce4906 100644
--- u-boot-4d3c95f.orig/include/configs/vision2.h
+++ u-boot-4d3c95f/include/configs/vision2.h
@@ -203,6 +203,7 @@
 /* 166 MHz DDR RAM */
 #define CONFIG_SYS_DDR_CLKSEL		0
 #define CONFIG_SYS_CLKTL_CBCDR		0x19239100
+#define CONFIG_SYS_MAIN_PWR_ON
 
 #define CONFIG_SYS_NO_FLASH