From patchwork Fri Aug 10 06:42:29 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guan Xuetao X-Patchwork-Id: 176411 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 1E1392C008E for ; Fri, 10 Aug 2012 17:19:46 +1000 (EST) Received: from localhost ([::1]:45625 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SzjVY-0000ko-Sd for incoming@patchwork.ozlabs.org; Fri, 10 Aug 2012 03:19:44 -0400 Received: from eggs.gnu.org ([208.118.235.92]:45251) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SzioL-00072V-7I for qemu-devel@nongnu.org; Fri, 10 Aug 2012 02:35:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SzioJ-00037O-Cw for qemu-devel@nongnu.org; Fri, 10 Aug 2012 02:35:05 -0400 Received: from mprc.pku.edu.cn ([162.105.203.9]:36941) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SzioI-00032h-IA for qemu-devel@nongnu.org; Fri, 10 Aug 2012 02:35:03 -0400 Received: from linuxdev-32 ([162.105.203.8]) by mprc.pku.edu.cn (8.13.8/8.13.8) with ESMTP id q7A6X3b2022881; Fri, 10 Aug 2012 14:33:03 +0800 Received: by linuxdev-32 (Postfix, from userid 1000) id F01EA14605BD; Fri, 10 Aug 2012 14:42:40 +0800 (CST) From: gxt@mprc.pku.edu.cn To: qemu-devel@nongnu.org Date: Fri, 10 Aug 2012 14:42:29 +0800 Message-Id: X-Mailer: git-send-email 1.7.0.4 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 162.105.203.9 Cc: blauwirbel@gmail.com, aliguori@us.ibm.com, gxt@mprc.pku.edu.cn, afaerber@suse.de, chenwj@iis.sinica.edu.tw Subject: [Qemu-devel] [PATCHv2 09/19] unicore32-softmmu: Add puv3 ostimer support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Guan Xuetao This patch adds puv3 ostimer support, include os timer device simulation and ptimer support in puv3 machine. Signed-off-by: Guan Xuetao --- default-configs/unicore32-softmmu.mak | 1 + hw/Makefile.objs | 1 + hw/puv3.c | 3 + hw/puv3_ost.c | 151 +++++++++++++++++++++++++++++++++ 4 files changed, 156 insertions(+), 0 deletions(-) create mode 100644 hw/puv3_ost.c diff --git a/default-configs/unicore32-softmmu.mak b/default-configs/unicore32-softmmu.mak index 726a338..4d4fbfc 100644 --- a/default-configs/unicore32-softmmu.mak +++ b/default-configs/unicore32-softmmu.mak @@ -1,2 +1,3 @@ # Default configuration for unicore32-softmmu CONFIG_PUV3=y +CONFIG_PTIMER=y diff --git a/hw/Makefile.objs b/hw/Makefile.objs index 50554b6..b96722a 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -68,6 +68,7 @@ hw-obj-$(CONFIG_XILINX_AXI) += xilinx_axienet.o # PKUnity SoC devices hw-obj-$(CONFIG_PUV3) += puv3_intc.o +hw-obj-$(CONFIG_PUV3) += puv3_ost.o # PCI watchdog devices hw-obj-$(CONFIG_PCI) += wdt_i6300esb.o diff --git a/hw/puv3.c b/hw/puv3.c index 2870455..5a8a27c 100644 --- a/hw/puv3.c +++ b/hw/puv3.c @@ -46,6 +46,9 @@ static void puv3_soc_init(CPUUniCore32State *env) for (i = 0; i < PUV3_IRQS_NR; i++) { irqs[i] = qdev_get_gpio_in(dev, i); } + + /* Initialize minimal necessary devices for kernel booting */ + sysbus_create_simple("puv3_ost", PUV3_OST_BASE, irqs[PUV3_IRQS_OST0]); } static void puv3_board_init(CPUUniCore32State *env, ram_addr_t ram_size) diff --git a/hw/puv3_ost.c b/hw/puv3_ost.c new file mode 100644 index 0000000..dd30cad --- /dev/null +++ b/hw/puv3_ost.c @@ -0,0 +1,151 @@ +/* + * OSTimer device simulation in PKUnity SoC + * + * Copyright (C) 2010-2012 Guan Xuetao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation, or any later version. + * See the COPYING file in the top-level directory. + */ +#include "sysbus.h" +#include "ptimer.h" + +#undef DEBUG_PUV3 +#include "puv3.h" + +/* puv3 ostimer implementation. */ +typedef struct { + SysBusDevice busdev; + MemoryRegion iomem; + QEMUBH *bh; + qemu_irq irq; + ptimer_state *ptimer; + + uint32_t reg_OSMR0; + uint32_t reg_OSCR; + uint32_t reg_OSSR; + uint32_t reg_OIER; +} PUV3OSTState; + +static uint64_t puv3_ost_read(void *opaque, target_phys_addr_t offset, + unsigned size) +{ + PUV3OSTState *s = opaque; + uint32_t ret = 0; + + switch (offset) { + case 0x10: /* Counter Register */ + ret = s->reg_OSMR0 - (uint32_t)ptimer_get_count(s->ptimer); + break; + case 0x14: /* Status Register */ + ret = s->reg_OSSR; + break; + case 0x1c: /* Interrupt Enable Register */ + ret = s->reg_OIER; + break; + default: + DPRINTF("Bad offset %x\n", (int)offset); + } + DPRINTF("offset 0x%x, value 0x%x\n", offset, ret); + return ret; +} + +static void puv3_ost_write(void *opaque, target_phys_addr_t offset, + uint64_t value, unsigned size) +{ + PUV3OSTState *s = opaque; + + DPRINTF("offset 0x%x, value 0x%x\n", offset, value); + switch (offset) { + case 0x00: /* Match Register 0 */ + s->reg_OSMR0 = value; + if (s->reg_OSMR0 > s->reg_OSCR) { + ptimer_set_count(s->ptimer, s->reg_OSMR0 - s->reg_OSCR); + } else { + ptimer_set_count(s->ptimer, s->reg_OSMR0 + + (0xffffffff - s->reg_OSCR)); + } + ptimer_run(s->ptimer, 2); + break; + case 0x14: /* Status Register */ + assert(value == 0); + if (s->reg_OSSR) { + s->reg_OSSR = value; + qemu_irq_lower(s->irq); + } + break; + case 0x1c: /* Interrupt Enable Register */ + s->reg_OIER = value; + break; + default: + DPRINTF("Bad offset %x\n", (int)offset); + } +} + +static const MemoryRegionOps puv3_ost_ops = { + .read = puv3_ost_read, + .write = puv3_ost_write, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, + .endianness = DEVICE_NATIVE_ENDIAN, +}; + +static void puv3_ost_tick(void *opaque) +{ + PUV3OSTState *s = opaque; + + DPRINTF("ost hit when ptimer counter from 0x%x to 0x%x!\n", + s->reg_OSCR, s->reg_OSMR0); + + s->reg_OSCR = s->reg_OSMR0; + if (s->reg_OIER) { + s->reg_OSSR = 1; + qemu_irq_raise(s->irq); + } +} + +static int puv3_ost_init(SysBusDevice *dev) +{ + PUV3OSTState *s = FROM_SYSBUS(PUV3OSTState, dev); + + s->reg_OIER = 0; + s->reg_OSSR = 0; + s->reg_OSMR0 = 0; + s->reg_OSCR = 0; + + sysbus_init_irq(dev, &s->irq); + + s->bh = qemu_bh_new(puv3_ost_tick, s); + s->ptimer = ptimer_init(s->bh); + ptimer_set_freq(s->ptimer, 50 * 1000 * 1000); + + memory_region_init_io(&s->iomem, &puv3_ost_ops, s, "puv3_ost", + PUV3_REGS_OFFSET); + sysbus_init_mmio(dev, &s->iomem); + + return 0; +} + +static void puv3_ost_class_init(ObjectClass *klass, void *data) +{ + SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); + + sdc->init = puv3_ost_init; +} + +static const TypeInfo puv3_ost_info = { + .name = "puv3_ost", + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(PUV3OSTState), + .class_init = puv3_ost_class_init, +}; + +static void puv3_ost_register_type(void) +{ + type_register_static(&puv3_ost_info); +} + +type_init(puv3_ost_register_type)