From patchwork Fri Aug 10 06:42:31 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guan Xuetao X-Patchwork-Id: 176384 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 69AA72C0094 for ; Fri, 10 Aug 2012 17:03:01 +1000 (EST) Received: from localhost ([::1]:40477 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Szio9-0006b3-Gg for incoming@patchwork.ozlabs.org; Fri, 10 Aug 2012 02:34:53 -0400 Received: from eggs.gnu.org ([208.118.235.92]:37301) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Szio0-0006Oa-FY for qemu-devel@nongnu.org; Fri, 10 Aug 2012 02:34:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Szinx-000316-TW for qemu-devel@nongnu.org; Fri, 10 Aug 2012 02:34:44 -0400 Received: from mprc.pku.edu.cn ([162.105.203.9]:36927) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Szinx-000311-5E for qemu-devel@nongnu.org; Fri, 10 Aug 2012 02:34:41 -0400 Received: from linuxdev-32 ([162.105.203.8]) by mprc.pku.edu.cn (8.13.8/8.13.8) with ESMTP id q7A6X3Ud022883; Fri, 10 Aug 2012 14:33:03 +0800 Received: by linuxdev-32 (Postfix, from userid 1000) id 025CB14605C5; Fri, 10 Aug 2012 14:42:41 +0800 (CST) From: gxt@mprc.pku.edu.cn To: qemu-devel@nongnu.org Date: Fri, 10 Aug 2012 14:42:31 +0800 Message-Id: <2628343d8b2860f83c237b1faf7a16dc5fc06609.1344580628.git.gxt@mprc.pku.edu.cn> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 162.105.203.9 Cc: blauwirbel@gmail.com, aliguori@us.ibm.com, gxt@mprc.pku.edu.cn, afaerber@suse.de, chenwj@iis.sinica.edu.tw Subject: [Qemu-devel] [PATCHv2 11/19] unicore32-softmmu: Add puv3 pm support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Guan Xuetao This patch adds puv3 pm (power management) support, include pm device simulation for kernel booting. Thank Blue Swirl for pointing out the missing "break". v1->v2: Add initialization to ret in puv3_pm_read. Signed-off-by: Guan Xuetao --- hw/Makefile.objs | 1 + hw/puv3.c | 1 + hw/puv3_pm.c | 149 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 151 insertions(+), 0 deletions(-) create mode 100644 hw/puv3_pm.c diff --git a/hw/Makefile.objs b/hw/Makefile.objs index c6cc97b..e2a39d6 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -70,6 +70,7 @@ hw-obj-$(CONFIG_XILINX_AXI) += xilinx_axienet.o hw-obj-$(CONFIG_PUV3) += puv3_intc.o hw-obj-$(CONFIG_PUV3) += puv3_ost.o hw-obj-$(CONFIG_PUV3) += puv3_gpio.o +hw-obj-$(CONFIG_PUV3) += puv3_pm.o # PCI watchdog devices hw-obj-$(CONFIG_PCI) += wdt_i6300esb.o diff --git a/hw/puv3.c b/hw/puv3.c index 0354cf6..3a14b27 100644 --- a/hw/puv3.c +++ b/hw/puv3.c @@ -48,6 +48,7 @@ static void puv3_soc_init(CPUUniCore32State *env) } /* Initialize minimal necessary devices for kernel booting */ + sysbus_create_simple("puv3_pm", PUV3_PM_BASE, NULL); sysbus_create_simple("puv3_ost", PUV3_OST_BASE, irqs[PUV3_IRQS_OST0]); sysbus_create_varargs("puv3_gpio", PUV3_GPIO_BASE, irqs[PUV3_IRQS_GPIOLOW0], irqs[PUV3_IRQS_GPIOLOW1], diff --git a/hw/puv3_pm.c b/hw/puv3_pm.c new file mode 100644 index 0000000..621c968 --- /dev/null +++ b/hw/puv3_pm.c @@ -0,0 +1,149 @@ +/* + * Power Management device simulation in PKUnity SoC + * + * Copyright (C) 2010-2012 Guan Xuetao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation, or any later version. + * See the COPYING file in the top-level directory. + */ +#include "hw.h" +#include "sysbus.h" + +#undef DEBUG_PUV3 +#include "puv3.h" + +typedef struct { + SysBusDevice busdev; + MemoryRegion iomem; + + uint32_t reg_PMCR; + uint32_t reg_PCGR; + uint32_t reg_PLL_SYS_CFG; + uint32_t reg_PLL_DDR_CFG; + uint32_t reg_PLL_VGA_CFG; + uint32_t reg_DIVCFG; +} PUV3PMState; + +static uint64_t puv3_pm_read(void *opaque, target_phys_addr_t offset, + unsigned size) +{ + PUV3PMState *s = opaque; + uint32_t ret = 0; + + switch (offset) { + case 0x14: + ret = s->reg_PCGR; + break; + case 0x18: + ret = s->reg_PLL_SYS_CFG; + break; + case 0x1c: + ret = s->reg_PLL_DDR_CFG; + break; + case 0x20: + ret = s->reg_PLL_VGA_CFG; + break; + case 0x24: + ret = s->reg_DIVCFG; + break; + case 0x28: /* PLL SYS STATUS */ + ret = 0x00002401; + break; + case 0x2c: /* PLL DDR STATUS */ + ret = 0x00100c00; + break; + case 0x30: /* PLL VGA STATUS */ + ret = 0x00003801; + break; + case 0x34: /* DIV STATUS */ + ret = 0x22f52015; + break; + case 0x38: /* SW RESET */ + ret = 0x0; + break; + case 0x44: /* PLL DFC DONE */ + ret = 0x7; + break; + default: + DPRINTF("Bad offset 0x%x\n", offset); + } + DPRINTF("offset 0x%x, value 0x%x\n", offset, ret); + + return ret; +} + +static void puv3_pm_write(void *opaque, target_phys_addr_t offset, + uint64_t value, unsigned size) +{ + PUV3PMState *s = opaque; + + switch (offset) { + case 0x0: + s->reg_PMCR = value; + break; + case 0x14: + s->reg_PCGR = value; + break; + case 0x18: + s->reg_PLL_SYS_CFG = value; + break; + case 0x1c: + s->reg_PLL_DDR_CFG = value; + break; + case 0x20: + s->reg_PLL_VGA_CFG = value; + break; + case 0x24: + case 0x38: + break; + default: + DPRINTF("Bad offset 0x%x\n", offset); + } + DPRINTF("offset 0x%x, value 0x%x\n", offset, value); +} + +static const MemoryRegionOps puv3_pm_ops = { + .read = puv3_pm_read, + .write = puv3_pm_write, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, + .endianness = DEVICE_NATIVE_ENDIAN, +}; + +static int puv3_pm_init(SysBusDevice *dev) +{ + PUV3PMState *s = FROM_SYSBUS(PUV3PMState, dev); + + s->reg_PCGR = 0x0; + + memory_region_init_io(&s->iomem, &puv3_pm_ops, s, "puv3_pm", + PUV3_REGS_OFFSET); + sysbus_init_mmio(dev, &s->iomem); + + return 0; +} + +static void puv3_pm_class_init(ObjectClass *klass, void *data) +{ + SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); + + sdc->init = puv3_pm_init; +} + +static const TypeInfo puv3_pm_info = { + .name = "puv3_pm", + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(PUV3PMState), + .class_init = puv3_pm_class_init, +}; + +static void puv3_pm_register_type(void) +{ + type_register_static(&puv3_pm_info); +} + +type_init(puv3_pm_register_type)