From patchwork Fri Aug 10 06:42:30 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guan Xuetao X-Patchwork-Id: 176378 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id E50682C0094 for ; Fri, 10 Aug 2012 16:46:45 +1000 (EST) Received: from localhost ([::1]:42066 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Szioi-0007WV-Qb for incoming@patchwork.ozlabs.org; Fri, 10 Aug 2012 02:35:28 -0400 Received: from eggs.gnu.org ([208.118.235.92]:45317) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Szioa-0007NP-6K for qemu-devel@nongnu.org; Fri, 10 Aug 2012 02:35:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SzioY-0003Hr-Vr for qemu-devel@nongnu.org; Fri, 10 Aug 2012 02:35:20 -0400 Received: from mprc.pku.edu.cn ([162.105.203.9]:36952) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SzioY-0003Hf-8w for qemu-devel@nongnu.org; Fri, 10 Aug 2012 02:35:18 -0400 Received: from linuxdev-32 ([162.105.203.8]) by mprc.pku.edu.cn (8.13.8/8.13.8) with ESMTP id q7A6X3qK022882; Fri, 10 Aug 2012 14:33:03 +0800 Received: by linuxdev-32 (Postfix, from userid 1000) id F356314605C1; Fri, 10 Aug 2012 14:42:40 +0800 (CST) From: gxt@mprc.pku.edu.cn To: qemu-devel@nongnu.org Date: Fri, 10 Aug 2012 14:42:30 +0800 Message-Id: X-Mailer: git-send-email 1.7.0.4 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 162.105.203.9 Cc: blauwirbel@gmail.com, aliguori@us.ibm.com, gxt@mprc.pku.edu.cn, afaerber@suse.de, chenwj@iis.sinica.edu.tw Subject: [Qemu-devel] [PATCHv2 10/19] unicore32-softmmu: Add puv3 gpio support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Guan Xuetao This patch adds puv3 gpio (General Purpose Input/Output) support, include gpio device simulation and its interrupt support. v1->v2: Add initialization to ret in puv3_gpio_read. Signed-off-by: Guan Xuetao --- hw/Makefile.objs | 1 + hw/puv3.c | 6 ++ hw/puv3_gpio.c | 141 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 148 insertions(+), 0 deletions(-) create mode 100644 hw/puv3_gpio.c diff --git a/hw/Makefile.objs b/hw/Makefile.objs index b96722a..c6cc97b 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -69,6 +69,7 @@ hw-obj-$(CONFIG_XILINX_AXI) += xilinx_axienet.o # PKUnity SoC devices hw-obj-$(CONFIG_PUV3) += puv3_intc.o hw-obj-$(CONFIG_PUV3) += puv3_ost.o +hw-obj-$(CONFIG_PUV3) += puv3_gpio.o # PCI watchdog devices hw-obj-$(CONFIG_PCI) += wdt_i6300esb.o diff --git a/hw/puv3.c b/hw/puv3.c index 5a8a27c..0354cf6 100644 --- a/hw/puv3.c +++ b/hw/puv3.c @@ -49,6 +49,12 @@ static void puv3_soc_init(CPUUniCore32State *env) /* Initialize minimal necessary devices for kernel booting */ sysbus_create_simple("puv3_ost", PUV3_OST_BASE, irqs[PUV3_IRQS_OST0]); + sysbus_create_varargs("puv3_gpio", PUV3_GPIO_BASE, + irqs[PUV3_IRQS_GPIOLOW0], irqs[PUV3_IRQS_GPIOLOW1], + irqs[PUV3_IRQS_GPIOLOW2], irqs[PUV3_IRQS_GPIOLOW3], + irqs[PUV3_IRQS_GPIOLOW4], irqs[PUV3_IRQS_GPIOLOW5], + irqs[PUV3_IRQS_GPIOLOW6], irqs[PUV3_IRQS_GPIOLOW7], + irqs[PUV3_IRQS_GPIOHIGH], NULL); } static void puv3_board_init(CPUUniCore32State *env, ram_addr_t ram_size) diff --git a/hw/puv3_gpio.c b/hw/puv3_gpio.c new file mode 100644 index 0000000..9436e6c --- /dev/null +++ b/hw/puv3_gpio.c @@ -0,0 +1,141 @@ +/* + * GPIO device simulation in PKUnity SoC + * + * Copyright (C) 2010-2012 Guan Xuetao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation, or any later version. + * See the COPYING file in the top-level directory. + */ +#include "hw.h" +#include "sysbus.h" + +#undef DEBUG_PUV3 +#include "puv3.h" + +typedef struct { + SysBusDevice busdev; + MemoryRegion iomem; + qemu_irq irq[9]; + + uint32_t reg_GPLR; + uint32_t reg_GPDR; + uint32_t reg_GPIR; +} PUV3GPIOState; + +static uint64_t puv3_gpio_read(void *opaque, target_phys_addr_t offset, + unsigned size) +{ + PUV3GPIOState *s = opaque; + uint32_t ret = 0; + + switch (offset) { + case 0x00: + ret = s->reg_GPLR; + break; + case 0x04: + ret = s->reg_GPDR; + break; + case 0x20: + ret = s->reg_GPIR; + break; + default: + DPRINTF("Bad offset 0x%x\n", offset); + } + DPRINTF("offset 0x%x, value 0x%x\n", offset, ret); + + return ret; +} + +static void puv3_gpio_write(void *opaque, target_phys_addr_t offset, + uint64_t value, unsigned size) +{ + PUV3GPIOState *s = opaque; + + DPRINTF("offset 0x%x, value 0x%x\n", offset, value); + switch (offset) { + case 0x04: + s->reg_GPDR = value; + break; + case 0x08: + if (s->reg_GPDR & value) { + s->reg_GPLR |= value; + } else { + DPRINTF("Write gpio input port error!"); + } + break; + case 0x0c: + if (s->reg_GPDR & value) { + s->reg_GPLR &= ~value; + } else { + DPRINTF("Write gpio input port error!"); + } + break; + case 0x10: /* GRER */ + case 0x14: /* GFER */ + case 0x18: /* GEDR */ + break; + case 0x20: /* GPIR */ + s->reg_GPIR = value; + break; + default: + DPRINTF("Bad offset 0x%x\n", offset); + } +} + +static const MemoryRegionOps puv3_gpio_ops = { + .read = puv3_gpio_read, + .write = puv3_gpio_write, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, + .endianness = DEVICE_NATIVE_ENDIAN, +}; + +static int puv3_gpio_init(SysBusDevice *dev) +{ + PUV3GPIOState *s = FROM_SYSBUS(PUV3GPIOState, dev); + + s->reg_GPLR = 0; + s->reg_GPDR = 0; + + /* FIXME: these irqs not handled yet */ + sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW0]); + sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW1]); + sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW2]); + sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW3]); + sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW4]); + sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW5]); + sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW6]); + sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW7]); + sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOHIGH]); + + memory_region_init_io(&s->iomem, &puv3_gpio_ops, s, "puv3_gpio", + PUV3_REGS_OFFSET); + sysbus_init_mmio(dev, &s->iomem); + + return 0; +} + +static void puv3_gpio_class_init(ObjectClass *klass, void *data) +{ + SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); + + sdc->init = puv3_gpio_init; +} + +static const TypeInfo puv3_gpio_info = { + .name = "puv3_gpio", + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(PUV3GPIOState), + .class_init = puv3_gpio_class_init, +}; + +static void puv3_gpio_register_type(void) +{ + type_register_static(&puv3_gpio_info); +} + +type_init(puv3_gpio_register_type)