From patchwork Fri Aug 10 05:53:22 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dongsheng Wang X-Patchwork-Id: 176369 X-Patchwork-Delegate: galak@kernel.crashing.org Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id 0E3122C0147 for ; Fri, 10 Aug 2012 16:21:52 +1000 (EST) Received: from ch1outboundpool.messaging.microsoft.com (ch1ehsobe003.messaging.microsoft.com [216.32.181.183]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (Client CN "mail.global.frontbridge.com", Issuer "Microsoft Secure Server Authority" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 77CAB2C008D; Fri, 10 Aug 2012 16:21:17 +1000 (EST) Received: from mail84-ch1-R.bigfish.com (10.43.68.244) by CH1EHSOBE012.bigfish.com (10.43.70.62) with Microsoft SMTP Server id 14.1.225.23; Fri, 10 Aug 2012 06:21:12 +0000 Received: from mail84-ch1 (localhost [127.0.0.1]) by mail84-ch1-R.bigfish.com (Postfix) with ESMTP id 358933A0125; Fri, 10 Aug 2012 06:21:12 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275bh8275dhz2dh2a8h668h839he5bhf0ah107ah) Received: from mail84-ch1 (localhost.localdomain [127.0.0.1]) by mail84-ch1 (MessageSwitch) id 1344579669505548_32367; Fri, 10 Aug 2012 06:21:09 +0000 (UTC) Received: from CH1EHSMHS014.bigfish.com (snatpool2.int.messaging.microsoft.com [10.43.68.232]) by mail84-ch1.bigfish.com (Postfix) with ESMTP id 6FA0F48009F; Fri, 10 Aug 2012 06:21:09 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CH1EHSMHS014.bigfish.com (10.43.70.14) with Microsoft SMTP Server (TLS) id 14.1.225.23; Fri, 10 Aug 2012 06:21:09 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-004.039d.mgd.msft.net (10.84.1.14) with Microsoft SMTP Server (TLS) id 14.2.298.5; Fri, 10 Aug 2012 01:21:08 -0500 Received: from rock.am.freescale.net (rock.ap.freescale.net [10.193.20.106]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id q7A6L3pO017446; Thu, 9 Aug 2012 23:21:05 -0700 From: To: , Subject: [PATCH v2 1/2] powerpc/mpic: Add Open-PIC global timer document Date: Fri, 10 Aug 2012 13:53:22 +0800 Message-ID: <1344578002-8057-1-git-send-email-Dongsheng.wang@freescale.com> X-Mailer: git-send-email 1.7.5.1 MIME-Version: 1.0 X-OriginatorOrg: freescale.com Cc: devicetree-discuss@lists.ozlabs.org, Wang Dongsheng , scottwood@freescale.com, linuxppc-dev@lists.ozlabs.org, kumar.gala@freescale.com X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" From: Wang Dongsheng Add a description of the OPEN-PIC global timer in the OPEN-PIC document. Moidfy mpic-timer document. 1.Add a TFRR register region. This register is written by software to report the clocking frequency of the PIC timers. 2.Add a device_type. The global timer in line with the OPEN-PIC specification. Signed-off-by: Wang Dongsheng Signed-off-by: Li Yang --- Documentation/devicetree/bindings/open-pic.txt | 46 ++++++++++++++++++++ .../devicetree/bindings/powerpc/fsl/mpic-timer.txt | 21 +++++---- arch/powerpc/boot/dts/fsl/pq3-mpic-timer-B.dtsi | 7 ++- arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi | 7 ++- 4 files changed, 66 insertions(+), 15 deletions(-) diff --git a/Documentation/devicetree/bindings/open-pic.txt b/Documentation/devicetree/bindings/open-pic.txt index 909a902..045c2e9 100644 --- a/Documentation/devicetree/bindings/open-pic.txt +++ b/Documentation/devicetree/bindings/open-pic.txt @@ -92,6 +92,52 @@ Example 2: * References +* Open PIC global timers + +Required properties: +- compatible: "open-pic,global-timer" + +- reg : Contains two regions. The first is the timer frequency reporting + register for the group. The second is the main timer register bank + (GTCCR, GTBCR, GTVPR, GTDR). + +- available-ranges: use style section to define which + timer interrupts can be used. This property is optional; without this, + all timers within the group can be used. + +- interrupts: one interrupt per timer in the group, in order, starting + with timer zero. If available-ranges is present, only the interrupts + that correspond to available timers shall be present. + +* Examples + +Example 1: + + /* Note that this requires #interrupt-cells to be 4 */ + timer: timer@010f0 { + compatible = "open-pic,global-timer"; + device_type = "open-pic"; + reg = <0x010f0 4 0x01100 0x100>; + + /* Another AMP partition is using timer */ + available-ranges = <2 2>; + + interrupts = <2 0 3 0 + 3 0 3 0>; + }; + +Example 2: + + timer: timer@010f0 { + compatible = "open-pic,global-timer"; + device_type = "open-pic"; + reg = <0x010f0 4 0x01100 0x100>; + interrupts = <0 0 3 0 + 1 0 3 0 + 2 0 3 0 + 3 0 3 0>; + }; + [1] Power.org (TM) Standard for Embedded Power Architecture (TM) Platform Requirements (ePAPR), Version 1.0, July 2008. (http://www.power.org/resources/downloads/Power_ePAPR_APPROVED_v1.0.pdf) diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mpic-timer.txt b/Documentation/devicetree/bindings/powerpc/fsl/mpic-timer.txt index df41958..5aafca0 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/mpic-timer.txt +++ b/Documentation/devicetree/bindings/powerpc/fsl/mpic-timer.txt @@ -1,13 +1,14 @@ * Freescale MPIC timers Required properties: -- compatible: "fsl,mpic-global-timer" +- compatible: "fsl,global-timer" -- reg : Contains two regions. The first is the main timer register bank - (GTCCRxx, GTBCRxx, GTVPRxx, GTDRxx). The second is the timer control +- reg : Contains three regions. The first is the timer frequency reporting + register (TFRRx) for the group. The second is the main timer register + bank (GTCCRxx, GTBCRxx, GTVPRxx, GTDRxx). The third is the timer control register (TCRx) for the group. -- fsl,available-ranges: use style section to define which +- available-ranges: use style section to define which timer interrupts can be used. This property is optional; without this, all timers within the group can be used. @@ -18,19 +19,21 @@ Required properties: Example: /* Note that this requires #interrupt-cells to be 4 */ timer0: timer@41100 { - compatible = "fsl,mpic-global-timer"; - reg = <0x41100 0x100 0x41300 4>; + compatible = "fsl,global-timer"; + device_type = "open-pic"; + reg = <0x410f0 4 0x41100 0x100 0x41300 4>; /* Another AMP partition is using timers 0 and 1 */ - fsl,available-ranges = <2 2>; + available-ranges = <2 2>; interrupts = <2 0 3 0 3 0 3 0>; }; timer1: timer@42100 { - compatible = "fsl,mpic-global-timer"; - reg = <0x42100 0x100 0x42300 4>; + compatible = "fsl,global-timer"; + device_type = "open-pic"; + reg = <0x420f0 4 0x42100 0x100 0x42300 4>; interrupts = <4 0 3 0 5 0 3 0 6 0 3 0 diff --git a/arch/powerpc/boot/dts/fsl/pq3-mpic-timer-B.dtsi b/arch/powerpc/boot/dts/fsl/pq3-mpic-timer-B.dtsi index 8734cff..01cd33c 100644 --- a/arch/powerpc/boot/dts/fsl/pq3-mpic-timer-B.dtsi +++ b/arch/powerpc/boot/dts/fsl/pq3-mpic-timer-B.dtsi @@ -32,9 +32,10 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -timer@42100 { - compatible = "fsl,mpic-global-timer"; - reg = <0x42100 0x100 0x42300 4>; +timer@420f0 { + compatible = "fsl,global-timer"; + device_type = "open-pic"; + reg = <0x420f0 4 0x42100 0x100 0x42300 4>; interrupts = <4 0 3 0 5 0 3 0 6 0 3 0 diff --git a/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi index 71c30eb..c71d8e0 100644 --- a/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi +++ b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi @@ -44,9 +44,10 @@ mpic: pic@40000 { last-interrupt-source = <255>; }; -timer@41100 { - compatible = "fsl,mpic-global-timer"; - reg = <0x41100 0x100 0x41300 4>; +timer@410f0 { + compatible = "fsl,global-timer"; + device_type = "open-pic"; + reg = <0x410f0 4 0x41100 0x100 0x41300 4>; interrupts = <0 0 3 0 1 0 3 0 2 0 3 0