| Message ID | 1344572997-21250-1-git-send-email-sandhya.satyanarayana@ti.com |
|---|---|
| State | Accepted |
| Commit | 6995a2893718a54cbd255ea3dd9b6d7306e30cf2 |
| Delegated to: | Tom Rini |
| Headers | show |
On Fri, Aug 10, 2012 at 09:59:57AM +0530, Satyanarayana, Sandhya wrote: > This patch updates secure_emif_sdram_config with the > same value written to sdram_config during ddr3 initialization. > > During suspend/resume, this value is copied into sdram_config. > With this, a write to sdram_config at the end of resume sequence > which triggers an init sequence can be avoided. > > Without this register write in place, the DDR_RESET line goes > low for a few cycles during resume which is a violation of the > JEDEC spec. > > Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com> Queued to u-boot-ti/master, thanks!
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index cffd4ab..fd9fc4a 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -17,6 +17,7 @@ http://www.ti.com/ #include <asm/arch/cpu.h> #include <asm/arch/ddr_defs.h> +#include <asm/arch/sys_proto.h> #include <asm/io.h> #include <asm/emif.h> @@ -46,8 +47,10 @@ void config_sdram(const struct emif_regs *regs) { writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl); writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw); - if (regs->zq_config) + if (regs->zq_config){ writel(regs->zq_config, &emif_reg->emif_zq_config); + writel(regs->sdram_config, &cstat->secure_emif_sdram_config); + } writel(regs->sdram_config, &emif_reg->emif_sdram_config); } diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index de9ee91..6cfbef7 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -234,6 +234,8 @@ struct vtp_reg { struct ctrl_stat { unsigned int resv1[16]; unsigned int statusreg; /* ofset 0x40 */ + unsigned int resv2[51]; + unsigned int secure_emif_sdram_config; /* offset 0x0110 */ }; /* AM33XX GPIO registers */ diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h index 8a4b248..819ea65 100644 --- a/arch/arm/include/asm/arch-am33xx/sys_proto.h +++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -46,6 +46,7 @@ u32 get_sysboot_value(void); int print_cpuinfo(void); #endif +extern struct ctrl_stat *cstat; u32 get_device_type(void); void setup_clocks_for_console(void); void ddr_pll_config(unsigned int ddrpll_M);
This patch updates secure_emif_sdram_config with the same value written to sdram_config during ddr3 initialization. During suspend/resume, this value is copied into sdram_config. With this, a write to sdram_config at the end of resume sequence which triggers an init sequence can be avoided. Without this register write in place, the DDR_RESET line goes low for a few cycles during resume which is a violation of the JEDEC spec. Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com> --- :100644 100644 cffd4ab... fd9fc4a... M arch/arm/cpu/armv7/am33xx/ddr.c :100644 100644 de9ee91... 6cfbef7... M arch/arm/include/asm/arch-am33xx/cpu.h :100644 100644 8a4b248... 819ea65... M arch/arm/include/asm/arch-am33xx/sys_proto.h arch/arm/cpu/armv7/am33xx/ddr.c | 5 ++++- arch/arm/include/asm/arch-am33xx/cpu.h | 2 ++ arch/arm/include/asm/arch-am33xx/sys_proto.h | 1 + 3 files changed, 7 insertions(+), 1 deletions(-)