From patchwork Fri Aug 10 02:31:59 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 176334 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id CDB6D2C008B for ; Fri, 10 Aug 2012 12:33:08 +1000 (EST) Comment: DKIM? See http://www.dkim.org DKIM-Signature: v=1; a=rsa-sha1; c=relaxed/relaxed; d=gcc.gnu.org; s=default; x=1345170789; h=Comment: DomainKey-Signature:Received:Received:Received:Received:Received: Received:Received:Received:From:To:Cc:Subject:Date:Message-Id: In-Reply-To:References:Mailing-List:Precedence:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:Sender: Delivered-To; bh=ANROhQeGsFnWPyEuJiH6mwKxAio=; b=Rt3+XnItPeMjKaX +/iB4jfvzbZcypKpFafOPN6XEi7Hb0A8iNJf0HC9qxV2M7HqXRJiTPZLFoWpYV5E Fmmx7cm15EFHfs4SDYZGUAMlsufo1tLL3kM88iLVPPve3KTNWtoAuckNvnJQZAgY zg5pEVdfvgrbvut6vTRlQzcJ++54= Comment: DomainKeys? See http://antispam.yahoo.com/domainkeys DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=gcc.gnu.org; h=Received:Received:X-SWARE-Spam-Status:X-Spam-Check-By:Received:Received:Received:Received:Received:Received:From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:X-detected-operating-system:X-Received-From:X-IsSubscribed:Mailing-List:Precedence:List-Id:List-Unsubscribe:List-Archive:List-Post:List-Help:Sender:Delivered-To; b=lMcnnAo3WJXbkR/YHdDu4ryPz+f8uq27WaGlAdtuWDwNrfUZ2xAMar6eJXKFQ3 FH3Fw7f/vXOE3nEaCy/PkVXu3QmYzS9MxK+tz4fas/6NjJetL+ct3+BVZWerwQ40 gBIfkISq7aw0DUaSLTpxZ8LMfxLaoTDJ9qu3/zwUY28Qo=; Received: (qmail 13526 invoked by alias); 10 Aug 2012 02:32:38 -0000 Received: (qmail 13323 invoked by uid 22791); 10 Aug 2012 02:32:33 -0000 X-SWARE-Spam-Status: No, hits=-4.1 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM, KHOP_THREADED, RCVD_IN_DNSWL_HI, RCVD_IN_HOSTKARMA_W, SARE_PROLOSTOCK_SYM3, SPF_NEUTRAL, TW_XT X-Spam-Check-By: sourceware.org Received: from eggs.gnu.org (HELO eggs.gnu.org) (208.118.235.92) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 10 Aug 2012 02:32:16 +0000 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Szf1J-00017x-Qy for gcc-patches@gcc.gnu.org; Thu, 09 Aug 2012 22:32:16 -0400 Received: from mail-pb0-f47.google.com ([209.85.160.47]:55283) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Szf1J-00017M-HD for gcc-patches@gcc.gnu.org; Thu, 09 Aug 2012 22:32:13 -0400 Received: by pbcwy7 with SMTP id wy7so1833588pbc.20 for ; Thu, 09 Aug 2012 19:32:12 -0700 (PDT) Received: by 10.68.216.130 with SMTP id oq2mr8466093pbc.128.1344565932384; Thu, 09 Aug 2012 19:32:12 -0700 (PDT) Received: from anchor.twiddle.home ([173.160.232.49]) by mx.google.com with ESMTPS id ru4sm2299014pbc.66.2012.08.09.19.32.11 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 09 Aug 2012 19:32:11 -0700 (PDT) From: Richard Henderson To: uweigand@de.ibm.com Cc: gcc-patches@gcc.gnu.org Subject: [PATCH 5/7] s390: Implement extzv for z10 Date: Thu, 9 Aug 2012 19:31:59 -0700 Message-Id: <1344565921-27852-6-git-send-email-rth@redhat.com> In-Reply-To: <1344565921-27852-1-git-send-email-rth@redhat.com> References: <1344565921-27852-1-git-send-email-rth@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.47 X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org --- gcc/config/s390/predicates.md | 4 +++ gcc/config/s390/s390-protos.h | 1 + gcc/config/s390/s390.c | 16 ++++++++++++ gcc/config/s390/s390.md | 55 +++++++++++++++++++++++++++++++++++------ 4 files changed, 68 insertions(+), 8 deletions(-) diff --git a/gcc/config/s390/predicates.md b/gcc/config/s390/predicates.md index 333457d..e4632b9 100644 --- a/gcc/config/s390/predicates.md +++ b/gcc/config/s390/predicates.md @@ -101,6 +101,10 @@ return true; }) +(define_predicate "nonzero_shift_count_operand" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), 1, GET_MODE_BITSIZE (mode) - 1)"))) + ;; Return true if OP a valid operand for the LARL instruction. (define_predicate "larl_operand" diff --git a/gcc/config/s390/s390-protos.h b/gcc/config/s390/s390-protos.h index 79673d6..97c378f 100644 --- a/gcc/config/s390/s390-protos.h +++ b/gcc/config/s390/s390-protos.h @@ -110,5 +110,6 @@ extern bool s390_legitimate_address_without_index_p (rtx); extern bool s390_decompose_shift_count (rtx, rtx *, HOST_WIDE_INT *); extern int s390_branch_condition_mask (rtx); extern int s390_compare_and_branch_condition_mask (rtx); +extern bool s390_extzv_shift_ok (int, int, unsigned HOST_WIDE_INT); #endif /* RTX_CODE */ diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c index 4e22100..52138d7 100644 --- a/gcc/config/s390/s390.c +++ b/gcc/config/s390/s390.c @@ -1308,6 +1308,22 @@ s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in, int size, return true; } +/* Check whether a rotate of ROTL followed by an AND of CONTIG is equivalent + to a shift followed by the AND. In particular, CONTIG should not overlap + the (rotated) bit 0/bit 63 gap. */ + +bool +s390_extzv_shift_ok (int bitsize, int rotl, unsigned HOST_WIDE_INT contig) +{ + int pos, len; + bool ok; + + ok = s390_contiguous_bitmask_p (contig, bitsize, &pos, &len); + gcc_assert (ok); + + return (rotl <= pos || rotl >= pos + len + (64 - bitsize)); +} + /* Check whether we can (and want to) split a double-word move in mode MODE from SRC to DST into two single-word moves, moving the subword FIRST_SUBWORD first. */ diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index b6e1535..ae004ac 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -3298,15 +3298,25 @@ [(set_attr "op_type" "RS,RSY") (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) +(define_insn "extzv" + [(set (match_operand:DI 0 "register_operand" "=d") + (zero_extract:DI + (match_operand:DI 1 "register_operand" "d") + (match_operand 2 "const_int_operand" "") + (match_operand 3 "const_int_operand" ""))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_Z10" + "risbg\t%0,%1,63-%3-%2,128+63,63-%3-%2" + [(set_attr "op_type" "RIE") + (set_attr "z10prop" "z10_super_E1")]) -(define_insn_and_split "*extzv" +(define_insn_and_split "*pre_z10_extzv" [(set (match_operand:GPR 0 "register_operand" "=d") (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS") - (match_operand 2 "const_int_operand" "n") + (match_operand 2 "nonzero_shift_count_operand" "") (const_int 0))) (clobber (reg:CC CC_REGNUM))] - "INTVAL (operands[2]) > 0 - && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)" + "!TARGET_Z10" "#" "&& reload_completed" [(parallel @@ -3324,14 +3334,13 @@ operands[3] = GEN_INT (mask); }) -(define_insn_and_split "*extv" +(define_insn_and_split "*pre_z10_extv" [(set (match_operand:GPR 0 "register_operand" "=d") (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS") - (match_operand 2 "const_int_operand" "n") + (match_operand 2 "nonzero_shift_count_operand" "") (const_int 0))) (clobber (reg:CC CC_REGNUM))] - "INTVAL (operands[2]) > 0 - && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)" + "!TARGET_Z10" "#" "&& reload_completed" [(parallel @@ -6034,6 +6043,36 @@ (clobber (reg:CC CC_REGNUM))])] "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") +;; These two are what combine generates for (ashift (zero_extract)). +(define_insn "*extzv__srl" + [(set (match_operand:DSI 0 "register_operand" "=d") + (and:DSI (lshiftrt:DSI + (match_operand:DSI 1 "register_operand" "d") + (match_operand:DSI 2 "nonzero_shift_count_operand" "")) + (match_operand:DSI 3 "contiguous_bitmask_operand" ""))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_Z10 + /* Note that even for the SImode pattern, the rotate is always DImode. */ + && s390_extzv_shift_ok (, 64 - INTVAL (operands[2]), + INTVAL (operands[3]))" + "risbg\t%0,%1,%3,128+%3,64-%2" + [(set_attr "op_type" "RIE") + (set_attr "z10prop" "z10_super_E1")]) + +(define_insn "*extzv__sll" + [(set (match_operand:DSI 0 "register_operand" "=d") + (and:DSI (ashift:DSI + (match_operand:DSI 1 "register_operand" "d") + (match_operand:DSI 2 "nonzero_shift_count_operand" "")) + (match_operand:DSI 3 "contiguous_bitmask_operand" ""))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_Z10 + && s390_extzv_shift_ok (, INTVAL (operands[2]), + INTVAL (operands[3]))" + "risbg\t%0,%1,%3,128+%3,%2" + [(set_attr "op_type" "RIE") + (set_attr "z10prop" "z10_super_E1")]) + ; ; andsi3 instruction pattern(s).