From patchwork Tue Aug 7 19:49:15 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Blue Swirl X-Patchwork-Id: 175776 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id B121B2C0092 for ; Wed, 8 Aug 2012 05:51:16 +1000 (EST) Received: from localhost ([::1]:47140 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SypoA-0008Dy-Tu for incoming@patchwork.ozlabs.org; Tue, 07 Aug 2012 15:51:14 -0400 Received: from eggs.gnu.org ([208.118.235.92]:44946) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Sypmr-0005OB-VR for qemu-devel@nongnu.org; Tue, 07 Aug 2012 15:49:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Sypmo-0006PT-7b for qemu-devel@nongnu.org; Tue, 07 Aug 2012 15:49:53 -0400 Received: from mail-ey0-f173.google.com ([209.85.215.173]:50572) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Sypmo-0006I1-1Q for qemu-devel@nongnu.org; Tue, 07 Aug 2012 15:49:50 -0400 Received: by mail-ey0-f173.google.com with SMTP id c13so660502eaa.4 for ; Tue, 07 Aug 2012 12:49:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :in-reply-to:references; bh=79Wy+Jwft3XfcvFkIEy7+HTTnMzVxQSAO2E5CFKtMgM=; b=mBo/egzVLyUtKCb6cyAzWtC6uoRpfdO8AlbQn7AR1iKJu3LTOUfsf9LhhGrZOq5Wr6 3xiBZc1snqdzwmuslf7a96tFFz/h6Gz42Zij5rnOxS0cwsB5Kz5McPOEkEwUICn8UAUp 0/W7NYddRQoqrD//H0OkwzJ1PZ7rCp/NHAAx7MnUosNq7xHBl+39vnlcda4DI4tGvFYV Jb3qjoV+Lff0jxa5cSbp7SKSoP5VSV8TAAjOd1YoH6uRPEyzNP4RxiMaaJGmLDn4Rqgq 9W42HvRhWegy7FO5FfzY1oHt8ouW0Ct0weZjAyBO6HGxilkTYwkBgcVSKJO18alvMG5V Edcg== Received: by 10.14.223.72 with SMTP id u48mr4279916eep.37.1344368989607; Tue, 07 Aug 2012 12:49:49 -0700 (PDT) Received: from localhost.localdomain (blueswirl.broker.freenet6.net. [2001:5c0:1400:b::d5a3]) by mx.google.com with ESMTPS id 8sm58685718eeg.16.2012.08.07.12.49.47 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 07 Aug 2012 12:49:48 -0700 (PDT) From: Blue Swirl To: qemu-devel@nongnu.org Date: Tue, 7 Aug 2012 19:49:15 +0000 Message-Id: X-Mailer: git-send-email 1.7.2.5 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.215.173 Cc: blauwirbel@gmail.com Subject: [Qemu-devel] [PATCH v2 7/9] x86: avoid AREG0 for misc helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add an explicit CPUX86State parameter instead of relying on AREG0. Signed-off-by: Blue Swirl --- target-i386/Makefile.objs | 1 - target-i386/helper.h | 40 ++++++++++++------------ target-i386/misc_helper.c | 77 +++++++++++++++++++++------------------------ target-i386/translate.c | 49 ++++++++++++++++------------ 4 files changed, 84 insertions(+), 83 deletions(-) diff --git a/target-i386/Makefile.objs b/target-i386/Makefile.objs index f843fe9..04e34f8 100644 --- a/target-i386/Makefile.objs +++ b/target-i386/Makefile.objs @@ -6,6 +6,5 @@ obj-$(CONFIG_KVM) += kvm.o hyperv.o obj-$(CONFIG_LINUX_USER) += ioport-user.o obj-$(CONFIG_BSD_USER) += ioport-user.o -$(obj)/misc_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS) $(obj)/mem_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS) $(obj)/seg_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS) diff --git a/target-i386/helper.h b/target-i386/helper.h index ec7edca..9a9c064 100644 --- a/target-i386/helper.h +++ b/target-i386/helper.h @@ -41,12 +41,12 @@ DEF_HELPER_4(lcall_protected, void, int, tl, int, int) DEF_HELPER_1(iret_real, void, int) DEF_HELPER_2(iret_protected, void, int, int) DEF_HELPER_2(lret_protected, void, int, int) -DEF_HELPER_1(read_crN, tl, int) -DEF_HELPER_2(write_crN, void, int, tl) -DEF_HELPER_1(lmsw, void, tl) +DEF_HELPER_2(read_crN, tl, env, int) +DEF_HELPER_3(write_crN, void, env, int, tl) +DEF_HELPER_2(lmsw, void, env, tl) DEF_HELPER_1(clts, void, env) -DEF_HELPER_2(movl_drN_T0, void, int, tl) -DEF_HELPER_1(invlpg, void, tl) +DEF_HELPER_3(movl_drN_T0, void, env, int, tl) +DEF_HELPER_2(invlpg, void, env, tl) DEF_HELPER_3(enter_level, void, int, int, tl) #ifdef TARGET_X86_64 @@ -58,10 +58,10 @@ DEF_HELPER_1(sysexit, void, int) DEF_HELPER_1(syscall, void, int) DEF_HELPER_1(sysret, void, int) #endif -DEF_HELPER_1(hlt, void, int) -DEF_HELPER_1(monitor, void, tl) -DEF_HELPER_1(mwait, void, int) -DEF_HELPER_0(debug, void) +DEF_HELPER_2(hlt, void, env, int) +DEF_HELPER_2(monitor, void, env, tl) +DEF_HELPER_2(mwait, void, env, int) +DEF_HELPER_1(debug, void, env) DEF_HELPER_1(reset_rf, void, env) DEF_HELPER_3(raise_interrupt, void, env, int, int) DEF_HELPER_2(raise_exception, void, env, int) @@ -72,22 +72,22 @@ DEF_HELPER_1(reset_inhibit_irq, void, env) DEF_HELPER_2(boundw, void, tl, int) DEF_HELPER_2(boundl, void, tl, int) DEF_HELPER_1(rsm, void, env) -DEF_HELPER_1(into, void, int) +DEF_HELPER_2(into, void, env, int) DEF_HELPER_1(cmpxchg8b, void, tl) #ifdef TARGET_X86_64 DEF_HELPER_1(cmpxchg16b, void, tl) #endif -DEF_HELPER_0(single_step, void) -DEF_HELPER_0(cpuid, void) -DEF_HELPER_0(rdtsc, void) -DEF_HELPER_0(rdtscp, void) -DEF_HELPER_0(rdpmc, void) -DEF_HELPER_0(rdmsr, void) -DEF_HELPER_0(wrmsr, void) +DEF_HELPER_1(single_step, void, env) +DEF_HELPER_1(cpuid, void, env) +DEF_HELPER_1(rdtsc, void, env) +DEF_HELPER_1(rdtscp, void, env) +DEF_HELPER_1(rdpmc, void, env) +DEF_HELPER_1(rdmsr, void, env) +DEF_HELPER_1(wrmsr, void, env) -DEF_HELPER_1(check_iob, void, i32) -DEF_HELPER_1(check_iow, void, i32) -DEF_HELPER_1(check_iol, void, i32) +DEF_HELPER_2(check_iob, void, env, i32) +DEF_HELPER_2(check_iow, void, env, i32) +DEF_HELPER_2(check_iol, void, env, i32) DEF_HELPER_2(outb, void, i32, i32) DEF_HELPER_1(inb, tl, i32) DEF_HELPER_2(outw, void, i32, i32) diff --git a/target-i386/misc_helper.c b/target-i386/misc_helper.c index 272a636..154601b 100644 --- a/target-i386/misc_helper.c +++ b/target-i386/misc_helper.c @@ -18,16 +18,11 @@ */ #include "cpu.h" -#include "dyngen-exec.h" #include "ioport.h" #include "helper.h" -#if !defined(CONFIG_USER_ONLY) -#include "softmmu_exec.h" -#endif /* !defined(CONFIG_USER_ONLY) */ - /* check if Port I/O is allowed in TSS */ -static inline void check_io(int addr, int size) +static inline void check_io(CPUX86State *env, int addr, int size) { int io_offset, val, mask; @@ -37,13 +32,13 @@ static inline void check_io(int addr, int size) env->tr.limit < 103) { goto fail; } - io_offset = lduw_kernel(env->tr.base + 0x66); + io_offset = cpu_lduw_kernel(env, env->tr.base + 0x66); io_offset += (addr >> 3); /* Note: the check needs two bytes */ if ((io_offset + 1) > env->tr.limit) { goto fail; } - val = lduw_kernel(env->tr.base + io_offset); + val = cpu_lduw_kernel(env, env->tr.base + io_offset); val >>= (addr & 7); mask = (1 << size) - 1; /* all bits must be zero to allow the I/O */ @@ -53,19 +48,19 @@ static inline void check_io(int addr, int size) } } -void helper_check_iob(uint32_t t0) +void helper_check_iob(CPUX86State *env, uint32_t t0) { - check_io(t0, 1); + check_io(env, t0, 1); } -void helper_check_iow(uint32_t t0) +void helper_check_iow(CPUX86State *env, uint32_t t0) { - check_io(t0, 2); + check_io(env, t0, 2); } -void helper_check_iol(uint32_t t0) +void helper_check_iol(CPUX86State *env, uint32_t t0) { - check_io(t0, 4); + check_io(env, t0, 4); } void helper_outb(uint32_t port, uint32_t data) @@ -98,7 +93,7 @@ target_ulong helper_inl(uint32_t port) return cpu_inl(port); } -void helper_into(int next_eip_addend) +void helper_into(CPUX86State *env, int next_eip_addend) { int eflags; @@ -108,7 +103,7 @@ void helper_into(int next_eip_addend) } } -void helper_single_step(void) +void helper_single_step(CPUX86State *env) { #ifndef CONFIG_USER_ONLY check_hw_breakpoints(env, 1); @@ -117,7 +112,7 @@ void helper_single_step(void) raise_exception(env, EXCP01_DB); } -void helper_cpuid(void) +void helper_cpuid(CPUX86State *env) { uint32_t eax, ebx, ecx, edx; @@ -131,20 +126,20 @@ void helper_cpuid(void) } #if defined(CONFIG_USER_ONLY) -target_ulong helper_read_crN(int reg) +target_ulong helper_read_crN(CPUX86State *env, int reg) { return 0; } -void helper_write_crN(int reg, target_ulong t0) +void helper_write_crN(CPUX86State *env, int reg, target_ulong t0) { } -void helper_movl_drN_T0(int reg, target_ulong t0) +void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0) { } #else -target_ulong helper_read_crN(int reg) +target_ulong helper_read_crN(CPUX86State *env, int reg) { target_ulong val; @@ -164,7 +159,7 @@ target_ulong helper_read_crN(int reg) return val; } -void helper_write_crN(int reg, target_ulong t0) +void helper_write_crN(CPUX86State *env, int reg, target_ulong t0) { cpu_svm_check_intercept_param(env, SVM_EXIT_WRITE_CR0 + reg, 0); switch (reg) { @@ -189,7 +184,7 @@ void helper_write_crN(int reg, target_ulong t0) } } -void helper_movl_drN_T0(int reg, target_ulong t0) +void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0) { int i; @@ -211,21 +206,21 @@ void helper_movl_drN_T0(int reg, target_ulong t0) } #endif -void helper_lmsw(target_ulong t0) +void helper_lmsw(CPUX86State *env, target_ulong t0) { /* only 4 lower bits of CR0 are modified. PE cannot be set to zero if already set to one. */ t0 = (env->cr[0] & ~0xe) | (t0 & 0xf); - helper_write_crN(0, t0); + helper_write_crN(env, 0, t0); } -void helper_invlpg(target_ulong addr) +void helper_invlpg(CPUX86State *env, target_ulong addr) { cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPG, 0); tlb_flush_page(env, addr); } -void helper_rdtsc(void) +void helper_rdtsc(CPUX86State *env) { uint64_t val; @@ -239,13 +234,13 @@ void helper_rdtsc(void) EDX = (uint32_t)(val >> 32); } -void helper_rdtscp(void) +void helper_rdtscp(CPUX86State *env) { - helper_rdtsc(); + helper_rdtsc(env); ECX = (uint32_t)(env->tsc_aux); } -void helper_rdpmc(void) +void helper_rdpmc(CPUX86State *env) { if ((env->cr[4] & CR4_PCE_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) { raise_exception(env, EXCP0D_GPF); @@ -258,15 +253,15 @@ void helper_rdpmc(void) } #if defined(CONFIG_USER_ONLY) -void helper_wrmsr(void) +void helper_wrmsr(CPUX86State *env) { } -void helper_rdmsr(void) +void helper_rdmsr(CPUX86State *env) { } #else -void helper_wrmsr(void) +void helper_wrmsr(CPUX86State *env) { uint64_t val; @@ -413,7 +408,7 @@ void helper_wrmsr(void) } } -void helper_rdmsr(void) +void helper_rdmsr(CPUX86State *env) { uint64_t val; @@ -554,7 +549,7 @@ void helper_rdmsr(void) } #endif -static void do_hlt(void) +static void do_hlt(CPUX86State *env) { env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */ env->halted = 1; @@ -562,15 +557,15 @@ static void do_hlt(void) cpu_loop_exit(env); } -void helper_hlt(int next_eip_addend) +void helper_hlt(CPUX86State *env, int next_eip_addend) { cpu_svm_check_intercept_param(env, SVM_EXIT_HLT, 0); EIP += next_eip_addend; - do_hlt(); + do_hlt(env); } -void helper_monitor(target_ulong ptr) +void helper_monitor(CPUX86State *env, target_ulong ptr) { if ((uint32_t)ECX != 0) { raise_exception(env, EXCP0D_GPF); @@ -579,7 +574,7 @@ void helper_monitor(target_ulong ptr) cpu_svm_check_intercept_param(env, SVM_EXIT_MONITOR, 0); } -void helper_mwait(int next_eip_addend) +void helper_mwait(CPUX86State *env, int next_eip_addend) { if ((uint32_t)ECX != 0) { raise_exception(env, EXCP0D_GPF); @@ -592,11 +587,11 @@ void helper_mwait(int next_eip_addend) /* more than one CPU: do not sleep because another CPU may wake this one */ } else { - do_hlt(); + do_hlt(env); } } -void helper_debug(void) +void helper_debug(CPUX86State *env) { env->exception_index = EXCP_DEBUG; cpu_loop_exit(env); diff --git a/target-i386/translate.c b/target-i386/translate.c index 840d281..a4c2ae0 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -740,9 +740,15 @@ static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip, state_saved = 1; tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); switch (ot) { - case 0: gen_helper_check_iob(cpu_tmp2_i32); break; - case 1: gen_helper_check_iow(cpu_tmp2_i32); break; - case 2: gen_helper_check_iol(cpu_tmp2_i32); break; + case 0: + gen_helper_check_iob(cpu_env, cpu_tmp2_i32); + break; + case 1: + gen_helper_check_iow(cpu_env, cpu_tmp2_i32); + break; + case 2: + gen_helper_check_iol(cpu_env, cpu_tmp2_i32); + break; } } if(s->flags & HF_SVMI_MASK) { @@ -2736,7 +2742,7 @@ static void gen_debug(DisasContext *s, target_ulong cur_eip) if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); gen_jmp_im(cur_eip); - gen_helper_debug(); + gen_helper_debug(cpu_env); s->is_jmp = DISAS_TB_JUMP; } @@ -2753,9 +2759,9 @@ static void gen_eob(DisasContext *s) gen_helper_reset_rf(cpu_env); } if (s->singlestep_enabled) { - gen_helper_debug(); + gen_helper_debug(cpu_env); } else if (s->tf) { - gen_helper_single_step(); + gen_helper_single_step(cpu_env); } else { tcg_gen_exit_tb(0); } @@ -6832,7 +6838,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); gen_jmp_im(pc_start - s->cs_base); - gen_helper_into(tcg_const_i32(s->pc - pc_start)); + gen_helper_into(cpu_env, tcg_const_i32(s->pc - pc_start)); break; #ifdef WANT_ICEBP case 0xf1: /* icebp (undocumented, exits to external debugger) */ @@ -6989,9 +6995,9 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_op_set_cc_op(s->cc_op); gen_jmp_im(pc_start - s->cs_base); if (b & 2) { - gen_helper_rdmsr(); + gen_helper_rdmsr(cpu_env); } else { - gen_helper_wrmsr(); + gen_helper_wrmsr(cpu_env); } } break; @@ -7001,7 +7007,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_jmp_im(pc_start - s->cs_base); if (use_icount) gen_io_start(); - gen_helper_rdtsc(); + gen_helper_rdtsc(cpu_env); if (use_icount) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); @@ -7011,7 +7017,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); gen_jmp_im(pc_start - s->cs_base); - gen_helper_rdpmc(); + gen_helper_rdpmc(cpu_env); break; case 0x134: /* sysenter */ /* For Intel SYSENTER is valid on 64-bit */ @@ -7065,7 +7071,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); gen_jmp_im(pc_start - s->cs_base); - gen_helper_cpuid(); + gen_helper_cpuid(cpu_env); break; case 0xf4: /* hlt */ if (s->cpl != 0) { @@ -7074,7 +7080,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); gen_jmp_im(pc_start - s->cs_base); - gen_helper_hlt(tcg_const_i32(s->pc - pc_start)); + gen_helper_hlt(cpu_env, tcg_const_i32(s->pc - pc_start)); s->is_jmp = DISAS_TB_JUMP; } break; @@ -7186,7 +7192,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_op_andl_A0_ffff(); } gen_add_A0_ds_seg(s); - gen_helper_monitor(cpu_A0); + gen_helper_monitor(cpu_env, cpu_A0); break; case 1: /* mwait */ if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) || @@ -7194,7 +7200,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) goto illegal_op; gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); - gen_helper_mwait(tcg_const_i32(s->pc - pc_start)); + gen_helper_mwait(cpu_env, tcg_const_i32(s->pc - pc_start)); gen_eob(s); break; default: @@ -7334,7 +7340,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) } else { gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0); gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0); - gen_helper_lmsw(cpu_T[0]); + gen_helper_lmsw(cpu_env, cpu_T[0]); gen_jmp_im(s->pc - s->cs_base); gen_eob(s); } @@ -7348,7 +7354,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_op_set_cc_op(s->cc_op); gen_jmp_im(pc_start - s->cs_base); gen_lea_modrm(s, modrm, ®_addr, &offset_addr); - gen_helper_invlpg(cpu_A0); + gen_helper_invlpg(cpu_env, cpu_A0); gen_jmp_im(s->pc - s->cs_base); gen_eob(s); } @@ -7383,7 +7389,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_jmp_im(pc_start - s->cs_base); if (use_icount) gen_io_start(); - gen_helper_rdtscp(); + gen_helper_rdtscp(cpu_env); if (use_icount) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); @@ -7565,11 +7571,12 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_jmp_im(pc_start - s->cs_base); if (b & 2) { gen_op_mov_TN_reg(ot, 0, rm); - gen_helper_write_crN(tcg_const_i32(reg), cpu_T[0]); + gen_helper_write_crN(cpu_env, tcg_const_i32(reg), + cpu_T[0]); gen_jmp_im(s->pc - s->cs_base); gen_eob(s); } else { - gen_helper_read_crN(cpu_T[0], tcg_const_i32(reg)); + gen_helper_read_crN(cpu_T[0], cpu_env, tcg_const_i32(reg)); gen_op_mov_reg_T0(ot, rm); } break; @@ -7598,7 +7605,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (b & 2) { gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg); gen_op_mov_TN_reg(ot, 0, rm); - gen_helper_movl_drN_T0(tcg_const_i32(reg), cpu_T[0]); + gen_helper_movl_drN_T0(cpu_env, tcg_const_i32(reg), cpu_T[0]); gen_jmp_im(s->pc - s->cs_base); gen_eob(s); } else {