From patchwork Tue Aug 7 13:51:16 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 175639 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 050C92C007F for ; Tue, 7 Aug 2012 23:56:57 +1000 (EST) Received: from localhost ([::1]:50144 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SykHG-0002yL-8C for incoming@patchwork.ozlabs.org; Tue, 07 Aug 2012 09:56:54 -0400 Received: from eggs.gnu.org ([208.118.235.92]:40696) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SykGz-0002fS-JW for qemu-devel@nongnu.org; Tue, 07 Aug 2012 09:56:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SykGx-0003lN-IV for qemu-devel@nongnu.org; Tue, 07 Aug 2012 09:56:37 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:34365) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SykGx-0003lI-Az for qemu-devel@nongnu.org; Tue, 07 Aug 2012 09:56:35 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SykBo-00056s-TU; Tue, 07 Aug 2012 14:51:16 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 7 Aug 2012 14:51:16 +0100 Message-Id: <1344347476-19613-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1344347476-19613-1-git-send-email-peter.maydell@linaro.org> References: <1344347476-19613-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 81.2.115.146 Cc: patches@linaro.org Subject: [Qemu-devel] [PATCH 2/2] target-arm: Reinstate display of VFP registers in cpu_dump_state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Reinstate the display of VFP registers in cpu_dump_state(), if the CPU has them (this code had been #if 0'd out a for a long time). We drop the attempt ot display the values as floating point, since this makes assumptions about the host 'float' and 'double' formats and is not done by eg the i386 cpu_dump_state(). This display is gated on the CPU_DUMP_FPU flag, as for x86. Signed-off-by: Peter Maydell --- target-arm/translate.c | 42 ++++++++++++++++-------------------------- 1 file changed, 16 insertions(+), 26 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index 29008a4..1ada5fc 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -9970,19 +9970,6 @@ void cpu_dump_state(CPUARMState *env, FILE *f, fprintf_function cpu_fprintf, int flags) { int i; -#if 0 - union { - uint32_t i; - float s; - } s0, s1; - CPU_DoubleU d; - /* ??? This assumes float64 and double have the same layout. - Oh well, it's only debug dumps. */ - union { - float64 f64; - double d; - } d0; -#endif uint32_t psr; for(i=0;i<16;i++) { @@ -10002,20 +9989,23 @@ void cpu_dump_state(CPUARMState *env, FILE *f, fprintf_function cpu_fprintf, psr & CPSR_T ? 'T' : 'A', cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26); -#if 0 - for (i = 0; i < 16; i++) { - d.d = env->vfp.regs[i]; - s0.i = d.l.lower; - s1.i = d.l.upper; - d0.f64 = d.d; - cpu_fprintf(f, "s%02d=%08x(%8g) s%02d=%08x(%8g) d%02d=%08x%08x(%8g)\n", - i * 2, (int)s0.i, s0.s, - i * 2 + 1, (int)s1.i, s1.s, - i, (int)(uint32_t)d.l.upper, (int)(uint32_t)d.l.lower, - d0.d); + if (flags & CPU_DUMP_FPU) { + int numvfpregs = 0; + if (arm_feature(env, ARM_FEATURE_VFP)) { + numvfpregs += 16; + } + if (arm_feature(env, ARM_FEATURE_VFP3)) { + numvfpregs += 16; + } + for (i = 0; i < numvfpregs; i++) { + uint64_t v = float64_val(env->vfp.regs[i]); + cpu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", + i * 2, (uint32_t)v, + i * 2 + 1, (uint32_t)(v >> 32), + i, v); + } + cpu_fprintf(f, "FPSCR: %08x\n", (int)env->vfp.xregs[ARM_VFP_FPSCR]); } - cpu_fprintf(f, "FPSCR: %08x\n", (int)env->vfp.xregs[ARM_VFP_FPSCR]); -#endif } void restore_state_to_opc(CPUARMState *env, TranslationBlock *tb, int pc_pos)