From patchwork Tue Aug 7 10:00:43 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guan Xuetao X-Patchwork-Id: 175560 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 067A12C0082 for ; Tue, 7 Aug 2012 19:54:19 +1000 (EST) Received: from localhost ([::1]:54576 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SygUT-0000MS-5l for incoming@patchwork.ozlabs.org; Tue, 07 Aug 2012 05:54:17 -0400 Received: from eggs.gnu.org ([208.118.235.92]:49582) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SygUD-0000AJ-Jf for qemu-devel@nongnu.org; Tue, 07 Aug 2012 05:54:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SygU7-0004Bc-Jg for qemu-devel@nongnu.org; Tue, 07 Aug 2012 05:54:01 -0400 Received: from mprc.pku.edu.cn ([162.105.203.9]:55125) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SygU6-0004BI-ON for qemu-devel@nongnu.org; Tue, 07 Aug 2012 05:53:55 -0400 Received: from linuxdev-32 ([162.105.203.8]) by mprc.pku.edu.cn (8.13.8/8.13.8) with ESMTP id q779qKO3005574; Tue, 7 Aug 2012 17:52:20 +0800 Received: by linuxdev-32 (Postfix, from userid 1000) id 4FD091460394; Tue, 7 Aug 2012 18:01:03 +0800 (CST) From: gxt@mprc.pku.edu.cn To: qemu-devel@nongnu.org Date: Tue, 7 Aug 2012 18:00:43 +0800 Message-Id: <80c514e3f8dd85e7386d229e2d42149886fb13ae.1344333363.git.gxt@mprc.pku.edu.cn> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 162.105.203.9 Cc: aliguoli@us.ibm.com, blauwirbel@gmail.com, gxt@mprc.pku.edu.cn, afaerber@suse.de, chenwj@iis.sinica.edu.tw Subject: [Qemu-devel] [PATCH 03/19] unicore32-softmmu: Make UniCore32 cpuid & exceptions correct and runable X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Guan Xuetao This patch initializes the cpuid to exactly correct value because linux kernel will check it. In addition, the exception types are specified in proper situations. Then it could make exceptions generated correctly and timely. Signed-off-by: Guan Xuetao --- cpu-exec.c | 1 + linux-user/main.c | 3 ++- target-unicore32/cpu.c | 19 ++++++++++++++----- target-unicore32/cpu.h | 14 ++++++++------ 4 files changed, 25 insertions(+), 12 deletions(-) diff --git a/cpu-exec.c b/cpu-exec.c index 543460c..6c4e516 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -447,6 +447,7 @@ int cpu_exec(CPUArchState *env) #elif defined(TARGET_UNICORE32) if (interrupt_request & CPU_INTERRUPT_HARD && !(env->uncached_asr & ASR_I)) { + env->exception_index = UC32_EXCP_INTR; do_interrupt(env); next_tb = 0; } diff --git a/linux-user/main.c b/linux-user/main.c index 53714de..9d921aa 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -958,7 +958,8 @@ void cpu_loop(CPUUniCore32State *env) } } break; - case UC32_EXCP_TRAP: + case UC32_EXCP_DTRAP: + case UC32_EXCP_ITRAP: info.si_signo = SIGSEGV; info.si_errno = 0; /* XXX: check env->error_code */ diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c index de63f58..3425bbe 100644 --- a/target-unicore32/cpu.c +++ b/target-unicore32/cpu.c @@ -1,7 +1,7 @@ /* * QEMU UniCore32 CPU * - * Copyright (c) 2010-2011 GUAN Xue-tao + * Copyright (c) 2010-2012 Guan Xuetao * Copyright (c) 2012 SUSE LINUX Products GmbH * * This program is free software; you can redistribute it and/or modify @@ -32,13 +32,16 @@ static void unicore_ii_cpu_initfn(Object *obj) UniCore32CPU *cpu = UNICORE32_CPU(obj); CPUUniCore32State *env = &cpu->env; - env->cp0.c0_cpuid = 0x40010863; + env->cp0.c0_cpuid = 0x4d000863; + env->cp0.c0_cachetype = 0x0d152152; + env->cp0.c1_sys = 0x2000; + env->cp0.c2_base = 0x0; + env->cp0.c3_faultstatus = 0x0; + env->cp0.c4_faultaddr = 0x0; + env->ucf64.xregs[UC32_UCF64_FPSCR] = 0; set_feature(env, UC32_HWCAP_CMOV); set_feature(env, UC32_HWCAP_UCF64); - env->ucf64.xregs[UC32_UCF64_FPSCR] = 0; - env->cp0.c0_cachetype = 0x1dd20d2; - env->cp0.c1_sys = 0x00090078; } static void uc32_any_cpu_initfn(Object *obj) @@ -47,6 +50,7 @@ static void uc32_any_cpu_initfn(Object *obj) CPUUniCore32State *env = &cpu->env; env->cp0.c0_cpuid = 0xffffffff; + env->ucf64.xregs[UC32_UCF64_FPSCR] = 0; set_feature(env, UC32_HWCAP_CMOV); set_feature(env, UC32_HWCAP_UCF64); @@ -65,8 +69,13 @@ static void uc32_cpu_initfn(Object *obj) cpu_exec_init(env); env->cpu_model_str = object_get_typename(obj); +#ifdef CONFIG_USER_ONLY env->uncached_asr = ASR_MODE_USER; env->regs[31] = 0; +#else + env->uncached_asr = ASR_MODE_PRIV; + env->regs[31] = 0x03000000; +#endif tlb_flush(env, 1); } diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h index 81c14ff..d14fde5 100644 --- a/target-unicore32/cpu.h +++ b/target-unicore32/cpu.h @@ -1,15 +1,15 @@ /* * UniCore32 virtual CPU header * - * Copyright (C) 2010-2011 GUAN Xue-tao + * Copyright (C) 2010-2012 Guan Xuetao * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation, or (at your option) any * later version. See the COPYING file in the top-level directory. */ -#ifndef __CPU_UC32_H__ -#define __CPU_UC32_H__ +#ifndef QEMU_UNICORE32_CPU_H +#define QEMU_UNICORE32_CPU_H #define TARGET_LONG_BITS 32 #define TARGET_PAGE_BITS 12 @@ -89,8 +89,10 @@ typedef struct CPUUniCore32State { #define ASR_NZCV (ASR_N | ASR_Z | ASR_C | ASR_V) #define ASR_RESERVED (~(ASR_M | ASR_I | ASR_NZCV)) -#define UC32_EXCP_PRIV (ASR_MODE_PRIV) -#define UC32_EXCP_TRAP (ASR_MODE_TRAP) +#define UC32_EXCP_PRIV (1) +#define UC32_EXCP_ITRAP (2) +#define UC32_EXCP_DTRAP (3) +#define UC32_EXCP_INTR (4) /* Return the current ASR value. */ target_ulong cpu_asr_read(CPUUniCore32State *env1); @@ -189,4 +191,4 @@ static inline bool cpu_has_work(CPUUniCore32State *env) (CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB); } -#endif /* __CPU_UC32_H__ */ +#endif /* QEMU_UNICORE32_CPU_H */