Patchwork [U-Boot,03/16] Blackfin: Bf60x: support big cplb page

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Submitter Bob Liu
Date Aug. 7, 2012, 8:07 a.m.
Message ID <1344326875-348-3-git-send-email-lliubbo@gmail.com>
Download mbox | patch
Permalink /patch/175521/
State Superseded
Delegated to: Mike Frysinger
Headers show

Comments

Bob Liu - Aug. 7, 2012, 8:07 a.m.
Bf60x support 16K, 64K, 16M and 64M cplb pages, this patch add support for them.
So that bf609-ezkit can use it's 128M memory.

Signed-off-by: Bob Liu <lliubbo@gmail.com>
---
 arch/blackfin/include/asm/cplb.h                 |   13 +++++++++-
 arch/blackfin/include/asm/mach-common/bits/mpu.h |    6 ++++-
 arch/blackfin/lib/board.c                        |   28 ++++++++++++++++------
 include/configs/bf609-ezkit.h                    |    6 +----
 4 files changed, 39 insertions(+), 14 deletions(-)
Mike Frysinger - Aug. 8, 2012, 4:48 a.m.
On Tuesday 07 August 2012 04:07:42 Bob Liu wrote:
> Bf60x support 16K, 64K, 16M and 64M cplb pages, this patch add support for
> them. So that bf609-ezkit can use it's 128M memory.

"it's" -> "its"

>  arch/blackfin/include/asm/cplb.h                 |   13 +++++++++-
>  arch/blackfin/include/asm/mach-common/bits/mpu.h |    6 ++++-
>  arch/blackfin/lib/board.c                        |   28
> ++++++++++++++++------ include/configs/bf609-ezkit.h                    | 
>   6 +----
>  4 files changed, 39 insertions(+), 14 deletions(-)
> 
> diff --git a/arch/blackfin/include/asm/cplb.h
> b/arch/blackfin/include/asm/cplb.h index cc21e93..5a0588b 100644
> --- a/arch/blackfin/include/asm/cplb.h
> +++ b/arch/blackfin/include/asm/cplb.h
> @@ -46,8 +46,11 @@
>  #define CPLB_IDOCACHE		CPLB_INOCACHE | CPLB_L1_CHBL
> 
>  /* Data Attibutes*/
> -
> +#if defined(__ADSPBF60x__)
> +#define SDRAM_IGENERIC          (PAGE_SIZE_16MB | CPLB_L1_CHBL |
> CPLB_USER_RD | CPLB_VALID)
> +#else
>  #define SDRAM_IGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL |
>  CPLB_USER_RD | CPLB_VALID)
> +#endif

many of these ifdefs are largely the same thing.  add a define at the top like:
#ifdef __ADSPBF60x__
# define PAGE_SIZE_MAX PAGE_SIZE_16MB
#else
# define PAGE_SIZE_MAX PAGE_SIZE_14MB
#endif

and then use that in all the other places.  this way you don't need to 
duplicate the vast majority of the content.

> --- a/arch/blackfin/include/asm/mach-common/bits/mpu.h
> +++ b/arch/blackfin/include/asm/mach-common/bits/mpu.h

this should get merged into the main cpu update patch i think

> --- a/arch/blackfin/lib/board.c
> +++ b/arch/blackfin/lib/board.c
> 
>  void init_cplbtables(void)
>  {
> ...
> +#if defined(__ADSPBF60x__)
> +	icplb_add(0x0, 0x0);

err, why ?

> +	dcplb_add(CONFIG_SYS_FLASH_BASE, PAGE_SIZE_16MB | CPLB_DIRTY |
> +			CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID);

can't you use SDRAM_EBIU/SDRAM_INON_CHBL like BF5xx ?  that's what the code 
below is for:
> +#ifndef __ADSPBF60x__
>  	icplb_add(0x20000000, SDRAM_INON_CHBL);
>  	dcplb_add(0x20000000, SDRAM_EBIU);
>  	++i;
> +#endif

this is the async memory blocks ...

> +	cplb_page_size = (4 * 1024 * 1024);
> +	cplb_page_mask = (~(cplb_page_size - 1));

why only use CPLBs of 4 megs for external memory on BF60x ?  you would want to 
maximize the usage of 16MiB to reduce CPLB overhead.

> --- a/include/configs/bf609-ezkit.h
> +++ b/include/configs/bf609-ezkit.h
> @@ -62,11 +62,10 @@
>  #define CONFIG_BFIN_GET_SCLK0 (get_sclk()/CONFIG_SCLK0_DIV)
>  #define CONFIG_BFIN_GET_SCLK1 (get_sclk()/CONFIG_SCLK1_DIV)
> 
> -
>  /*
>   * Memory Settings
>   */
> -#define CONFIG_MEM_SIZE		32
> +#define CONFIG_MEM_SIZE		128
> 
>  #define CONFIG_SMC_GCTL_VAL	0x00000010
>  #define CONFIG_SMC_B1CTL_VAL	0x01002001
> @@ -76,9 +75,6 @@
>  #define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
>  #define CONFIG_SYS_MALLOC_LEN	(256 * 1024)
> 
> -#define CONFIG_ICACHE_OFF
> -#define CONFIG_DCACHE_OFF
> -
>  /*
>   * Network Settings
>   */

once the CPLB code is updated, you can squash this into the new bf609-ezkit 
patch
-mike
Bob Liu - Aug. 20, 2012, 8 a.m.
On Wed, Aug 8, 2012 at 12:48 PM, Mike Frysinger <vapier@gentoo.org> wrote:
> On Tuesday 07 August 2012 04:07:42 Bob Liu wrote:
>> Bf60x support 16K, 64K, 16M and 64M cplb pages, this patch add support for
>> them. So that bf609-ezkit can use it's 128M memory.
>
> "it's" -> "its"
>
>>  arch/blackfin/include/asm/cplb.h                 |   13 +++++++++-
>>  arch/blackfin/include/asm/mach-common/bits/mpu.h |    6 ++++-
>>  arch/blackfin/lib/board.c                        |   28
>> ++++++++++++++++------ include/configs/bf609-ezkit.h                    |
>>   6 +----
>>  4 files changed, 39 insertions(+), 14 deletions(-)
>>
>> diff --git a/arch/blackfin/include/asm/cplb.h
>> b/arch/blackfin/include/asm/cplb.h index cc21e93..5a0588b 100644
>> --- a/arch/blackfin/include/asm/cplb.h
>> +++ b/arch/blackfin/include/asm/cplb.h
>> @@ -46,8 +46,11 @@
>>  #define CPLB_IDOCACHE                CPLB_INOCACHE | CPLB_L1_CHBL
>>
>>  /* Data Attibutes*/
>> -
>> +#if defined(__ADSPBF60x__)
>> +#define SDRAM_IGENERIC          (PAGE_SIZE_16MB | CPLB_L1_CHBL |
>> CPLB_USER_RD | CPLB_VALID)
>> +#else
>>  #define SDRAM_IGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL |
>>  CPLB_USER_RD | CPLB_VALID)
>> +#endif
>
> many of these ifdefs are largely the same thing.  add a define at the top like:
> #ifdef __ADSPBF60x__
> # define PAGE_SIZE_MAX PAGE_SIZE_16MB
> #else
> # define PAGE_SIZE_MAX PAGE_SIZE_14MB
> #endif
>
> and then use that in all the other places.  this way you don't need to
> duplicate the vast majority of the content.

Okay.

>
>> --- a/arch/blackfin/include/asm/mach-common/bits/mpu.h
>> +++ b/arch/blackfin/include/asm/mach-common/bits/mpu.h
>
> this should get merged into the main cpu update patch i think
>
>> --- a/arch/blackfin/lib/board.c
>> +++ b/arch/blackfin/lib/board.c
>>
>>  void init_cplbtables(void)
>>  {
>> ...
>> +#if defined(__ADSPBF60x__)
>> +     icplb_add(0x0, 0x0);
>
> err, why ?

Because other place use value "i" for both icplb and dcplb this make
them consistent.

>
>> +     dcplb_add(CONFIG_SYS_FLASH_BASE, PAGE_SIZE_16MB | CPLB_DIRTY |
>> +                     CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID);
>
> can't you use SDRAM_EBIU/SDRAM_INON_CHBL like BF5xx ?  that's what the code
> below is for:
>> +#ifndef __ADSPBF60x__
>>       icplb_add(0x20000000, SDRAM_INON_CHBL);
>>       dcplb_add(0x20000000, SDRAM_EBIU);
>>       ++i;
>> +#endif
>
> this is the async memory blocks ...
>
>> +     cplb_page_size = (4 * 1024 * 1024);
>> +     cplb_page_mask = (~(cplb_page_size - 1));
>
> why only use CPLBs of 4 megs for external memory on BF60x ?  you would want to
> maximize the usage of 16MiB to reduce CPLB overhead.

Bf60x will reinit cplb_page_size/mask behind.

>
>> --- a/include/configs/bf609-ezkit.h
>> +++ b/include/configs/bf609-ezkit.h
>> @@ -62,11 +62,10 @@
>>  #define CONFIG_BFIN_GET_SCLK0 (get_sclk()/CONFIG_SCLK0_DIV)
>>  #define CONFIG_BFIN_GET_SCLK1 (get_sclk()/CONFIG_SCLK1_DIV)
>>
>> -
>>  /*
>>   * Memory Settings
>>   */
>> -#define CONFIG_MEM_SIZE              32
>> +#define CONFIG_MEM_SIZE              128
>>
>>  #define CONFIG_SMC_GCTL_VAL  0x00000010
>>  #define CONFIG_SMC_B1CTL_VAL 0x01002001
>> @@ -76,9 +75,6 @@
>>  #define CONFIG_SYS_MONITOR_LEN       (256 * 1024)
>>  #define CONFIG_SYS_MALLOC_LEN        (256 * 1024)
>>
>> -#define CONFIG_ICACHE_OFF
>> -#define CONFIG_DCACHE_OFF
>> -
>>  /*
>>   * Network Settings
>>   */
>
> once the CPLB code is updated, you can squash this into the new bf609-ezkit
> patch

Okay.
Mike Frysinger - Aug. 23, 2012, 3:49 a.m.
On Monday 20 August 2012 04:00:21 Bob Liu wrote:
> On Wed, Aug 8, 2012 at 12:48 PM, Mike Frysinger wrote:
> > On Tuesday 07 August 2012 04:07:42 Bob Liu wrote:
> >> --- a/arch/blackfin/lib/board.c
> >> +++ b/arch/blackfin/lib/board.c
> >> 
> >>  void init_cplbtables(void)
> >>  {
> >> ...
> >> +#if defined(__ADSPBF60x__)
> >> +     icplb_add(0x0, 0x0);
> > 
> > err, why ?
> 
> Because other place use value "i" for both icplb and dcplb this make
> them consistent.

why not add an ICPLB entry for the same region you just added a DCPLB entry 
for ?  we can directly execute out of the flash memory region ...

> >> +     cplb_page_size = (4 * 1024 * 1024);
> >> +     cplb_page_mask = (~(cplb_page_size - 1));
> > 
> > why only use CPLBs of 4 megs for external memory on BF60x ?  you would
> > want to maximize the usage of 16MiB to reduce CPLB overhead.
> 
> Bf60x will reinit cplb_page_size/mask behind.

sorry, i don't understand what you mean
-mike

Patch

diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h
index cc21e93..5a0588b 100644
--- a/arch/blackfin/include/asm/cplb.h
+++ b/arch/blackfin/include/asm/cplb.h
@@ -46,8 +46,11 @@ 
 #define CPLB_IDOCACHE		CPLB_INOCACHE | CPLB_L1_CHBL
 
 /* Data Attibutes*/
-
+#if defined(__ADSPBF60x__)
+#define SDRAM_IGENERIC          (PAGE_SIZE_16MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
+#else
 #define SDRAM_IGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
+#endif
 #define SDRAM_IKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
 #define L1_IMEMORY              (PAGE_SIZE_1MB | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
 #define SDRAM_INON_CHBL         (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
@@ -59,14 +62,22 @@ 
 #endif
 
 #ifdef CONFIG_DCACHE_WB		/*Write Back Policy */
+#if defined(__ADSPBF60x__)
+#define SDRAM_DGENERIC          (PAGE_SIZE_16MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
+#else
 #define SDRAM_DGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
+#endif
 #define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
 #define SDRAM_DKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND)
 #define L1_DMEMORY              (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
 #define SDRAM_EBIU              (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
 
 #else				/*Write Through */
+#if defined(__ADSPBF60x__)
+#define SDRAM_DGENERIC          (PAGE_SIZE_16MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
+#else
 #define SDRAM_DGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
+#endif
 #define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
 #define SDRAM_DKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND)
 #define L1_DMEMORY              (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
diff --git a/arch/blackfin/include/asm/mach-common/bits/mpu.h b/arch/blackfin/include/asm/mach-common/bits/mpu.h
index 39998f8..d067ef9 100644
--- a/arch/blackfin/include/asm/mach-common/bits/mpu.h
+++ b/arch/blackfin/include/asm/mach-common/bits/mpu.h
@@ -70,7 +70,11 @@ 
 #define PAGE_SIZE_4KB		0x00010000	/* 4 KB page size */
 #define PAGE_SIZE_1MB		0x00020000	/* 1 MB page size */
 #define PAGE_SIZE_4MB		0x00030000	/* 4 MB page size */
-#define PAGE_SIZE_MASK		0x00030000	/* the bits for the page_size field */
+#define PAGE_SIZE_16KB		0x00040000	/* 16 KB page size */
+#define PAGE_SIZE_64KB		0x00050000	/* 64 KB page size */
+#define PAGE_SIZE_16MB		0x00060000	/* 16 MB page size */
+#define PAGE_SIZE_64MB		0x00070000	/* 64 MB page size */
+#define PAGE_SIZE_MASK		0x00070000	/* the bits for the page_size field */
 #define PAGE_SIZE_SHIFT		16
 #define CPLB_L1SRAM		0x00000020	/* 0=SRAM mapped in L1, 0=SRAM not mapped to L1 */
 #define CPLB_PORTPRIO		0x00000200	/* 0=low priority port, 1= high priority port */
diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c
index cfb38e8..4e44bf0 100644
--- a/arch/blackfin/lib/board.c
+++ b/arch/blackfin/lib/board.c
@@ -94,12 +94,12 @@  static void display_global_data(void)
 	printf("   \\-bi_flashoffset: %lx\n", bd->bi_flashoffset);
 }
 
-#define CPLB_PAGE_SIZE (4 * 1024 * 1024)
-#define CPLB_PAGE_MASK (~(CPLB_PAGE_SIZE - 1))
 void init_cplbtables(void)
 {
 	volatile uint32_t *ICPLB_ADDR, *ICPLB_DATA;
 	volatile uint32_t *DCPLB_ADDR, *DCPLB_DATA;
+	uint32_t cplb_page_size;
+	uint32_t cplb_page_mask;
 	uint32_t extern_memory;
 	size_t i;
 
@@ -127,12 +127,20 @@  void init_cplbtables(void)
 	icplb_add(0xFFA00000, L1_IMEMORY);
 	dcplb_add(0xFF800000, L1_DMEMORY);
 	++i;
+#if defined(__ADSPBF60x__)
+	icplb_add(0x0, 0x0);
+	dcplb_add(CONFIG_SYS_FLASH_BASE, PAGE_SIZE_16MB | CPLB_DIRTY | CPLB_SUPV_WR |
+			CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID);
+	++i;
+#endif
+	cplb_page_size = (4 * 1024 * 1024);
+	cplb_page_mask = (~(cplb_page_size - 1));
 
 	if (CONFIG_MEM_SIZE) {
 		uint32_t mbase = CONFIG_SYS_MONITOR_BASE;
 		uint32_t mend  = mbase + CONFIG_SYS_MONITOR_LEN;
-		mbase &= CPLB_PAGE_MASK;
-		mend &= CPLB_PAGE_MASK;
+		mbase &= cplb_page_mask;
+		mend &= cplb_page_mask;
 
 		icplb_add(mbase, SDRAM_IKERNEL);
 		dcplb_add(mbase, SDRAM_DKERNEL);
@@ -150,9 +158,11 @@  void init_cplbtables(void)
 		}
 	}
 
+#ifndef __ADSPBF60x__
 	icplb_add(0x20000000, SDRAM_INON_CHBL);
 	dcplb_add(0x20000000, SDRAM_EBIU);
 	++i;
+#endif
 
 	/* Add entries for the rest of external RAM up to the bootrom */
 	extern_memory = 0;
@@ -163,14 +173,18 @@  void init_cplbtables(void)
 	++i;
 	icplb_add(extern_memory, SDRAM_IKERNEL);
 	dcplb_add(extern_memory, SDRAM_DKERNEL);
-	extern_memory += CPLB_PAGE_SIZE;
+	extern_memory += cplb_page_size;
 	++i;
 #endif
 
-	while (i < 16 && extern_memory < (CONFIG_SYS_MONITOR_BASE & CPLB_PAGE_MASK)) {
+#if defined(__ADSPBF60x__)
+	cplb_page_size = (16 * 1024 * 1024);
+	cplb_page_mask = (~(cplb_page_size - 1));
+#endif
+	while (i < 16 && extern_memory < (CONFIG_SYS_MONITOR_BASE & cplb_page_mask)) {
 		icplb_add(extern_memory, SDRAM_IGENERIC);
 		dcplb_add(extern_memory, SDRAM_DGENERIC);
-		extern_memory += CPLB_PAGE_SIZE;
+		extern_memory += cplb_page_size;
 		++i;
 	}
 	while (i < 16) {
diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h
index 9b1f6c2..1fc2a18 100644
--- a/include/configs/bf609-ezkit.h
+++ b/include/configs/bf609-ezkit.h
@@ -62,11 +62,10 @@ 
 #define CONFIG_BFIN_GET_SCLK0 (get_sclk()/CONFIG_SCLK0_DIV)
 #define CONFIG_BFIN_GET_SCLK1 (get_sclk()/CONFIG_SCLK1_DIV)
 
-
 /*
  * Memory Settings
  */
-#define CONFIG_MEM_SIZE		32
+#define CONFIG_MEM_SIZE		128
 
 #define CONFIG_SMC_GCTL_VAL	0x00000010
 #define CONFIG_SMC_B1CTL_VAL	0x01002001
@@ -76,9 +75,6 @@ 
 #define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
 #define CONFIG_SYS_MALLOC_LEN	(256 * 1024)
 
-#define CONFIG_ICACHE_OFF
-#define CONFIG_DCACHE_OFF
-
 /*
  * Network Settings
  */