| Message ID | 1344326875-348-8-git-send-email-lliubbo@gmail.com |
|---|---|
| State | Superseded |
| Delegated to: | Mike Frysinger |
| Headers | show |
On Tuesday 07 August 2012 04:07:47 Bob Liu wrote: > --- a/arch/blackfin/lib/clocks.c > +++ b/arch/blackfin/lib/clocks.c > > +u_long get_dclk(void) > +{ > +#ifndef CONFIG_BFIN_GET_DCLK > + return _get_sclk(&cached_dclk); > +#else > + return CONFIG_BFIN_GET_DCLK; > +#endif > +} this looks like my incomplete hack where the implementation of clock lookups weren't finished. that was because at the time, the hardware blocks of the bf60x were not finished which means i couldn't query the MMRs to calculate the values. please implement this ... > --- a/include/configs/bf609-ezkit.h > +++ b/include/configs/bf609-ezkit.h > > #define CONFIG_BFIN_GET_SCLK (CONFIG_PLL_CLK/CONFIG_SYSCLK_DIV) > #define CONFIG_BFIN_GET_SCLK0 (get_sclk()/CONFIG_SCLK0_DIV) > #define CONFIG_BFIN_GET_SCLK1 (get_sclk()/CONFIG_SCLK1_DIV) > +#define CONFIG_BFIN_GET_DCLK (get_cclk()/CONFIG_DCLK_DIV) and then point all these hard coded defines. these existed purely for initial FPGA bring up and were not intended to be shipped as the final code. -mike
On Wed, Aug 8, 2012 at 1:04 PM, Mike Frysinger <vapier@gentoo.org> wrote: > On Tuesday 07 August 2012 04:07:47 Bob Liu wrote: >> --- a/arch/blackfin/lib/clocks.c >> +++ b/arch/blackfin/lib/clocks.c >> >> +u_long get_dclk(void) >> +{ >> +#ifndef CONFIG_BFIN_GET_DCLK >> + return _get_sclk(&cached_dclk); >> +#else >> + return CONFIG_BFIN_GET_DCLK; >> +#endif >> +} > > this looks like my incomplete hack where the implementation of clock lookups > weren't finished. that was because at the time, the hardware blocks of the > bf60x were not finished which means i couldn't query the MMRs to calculate the > values. please implement this ... Will be implemented. > >> --- a/include/configs/bf609-ezkit.h >> +++ b/include/configs/bf609-ezkit.h >> >> #define CONFIG_BFIN_GET_SCLK (CONFIG_PLL_CLK/CONFIG_SYSCLK_DIV) >> #define CONFIG_BFIN_GET_SCLK0 (get_sclk()/CONFIG_SCLK0_DIV) >> #define CONFIG_BFIN_GET_SCLK1 (get_sclk()/CONFIG_SCLK1_DIV) >> +#define CONFIG_BFIN_GET_DCLK (get_cclk()/CONFIG_DCLK_DIV) > > and then point all these hard coded defines. these existed purely for initial > FPGA bring up and were not intended to be shipped as the final code. Will be updated. Thank you
diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c index 4e44bf0..e03bd57 100644 --- a/arch/blackfin/lib/board.c +++ b/arch/blackfin/lib/board.c @@ -311,7 +311,13 @@ void board_init_f(ulong bootflag) printf("Clock: VCO: %s MHz, ", strmhz(buf, get_vco())); printf("Core: %s MHz, ", strmhz(buf, get_cclk())); +#if defined(__ADSPBF60x__) + printf("System0: %s MHz, ", strmhz(buf, get_sclk0())); + printf("System1: %s MHz, ", strmhz(buf, get_sclk1())); + printf("Dclk: %s MHz\n", strmhz(buf, get_dclk())); +#else printf("System: %s MHz\n", strmhz(buf, get_sclk())); +#endif if (CONFIG_MEM_SIZE) { printf("RAM: "); diff --git a/arch/blackfin/lib/clocks.c b/arch/blackfin/lib/clocks.c index f867123..519a3e1 100644 --- a/arch/blackfin/lib/clocks.c +++ b/arch/blackfin/lib/clocks.c @@ -79,7 +79,7 @@ u_long get_cclk(void) /* Get the System clock */ #ifdef CGU_DIV -static u_long cached_sclk_pll_div, cached_sclk, cached_sclk0, cached_sclk1; +static u_long cached_sclk_pll_div, cached_sclk, cached_sclk0, cached_sclk1, cached_dclk; static u_long _get_sclk(u_long *cache) { u_long div, ssel; @@ -132,6 +132,14 @@ u_long get_sclk1(void) #endif } +u_long get_dclk(void) +{ +#ifndef CONFIG_BFIN_GET_DCLK + return _get_sclk(&cached_dclk); +#else + return CONFIG_BFIN_GET_DCLK; +#endif +} #else u_long get_sclk(void) diff --git a/common/cmd_reginfo.c b/common/cmd_reginfo.c index bf94119..ef49017 100644 --- a/common/cmd_reginfo.c +++ b/common/cmd_reginfo.c @@ -226,6 +226,23 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("\tEBIU_SDSTAT: 0x%04x EBIU_SDGCTL: 0x%08x\n", bfin_read_EBIU_SDSTAT(), bfin_read_EBIU_SDGCTL()); # endif +#else + puts("\nCGU Registers\n"); + printf("\tCGU_DIV: 0x%08x CGU_CTL: 0x%08x\n", + bfin_read_CGU_DIV(), bfin_read_CGU_CTL()); + printf("\tCGU_STAT: 0x%08x CGU_LOCKCNT: 0x%08x\n", + bfin_read_CGU_STAT(), bfin_read_CGU_CLKOUTSEL()); + + puts("\nSMC DDR Registers\n"); + printf("\tDDR_CFG: 0x%08x DDR_TR0: 0x%08x\n", + bfin_read_DMC0_CFG(), bfin_read_DMC0_TR0()); + printf("\tDDR_TR1: 0x%08x DDR_TR2: 0x%08x\n", + bfin_read_DMC0_TR1(), bfin_read_DMC0_TR2()); + printf("\tDDR_MR: 0x%08x DDR_EMR1: 0x%08x\n", + bfin_read_DMC0_MR(), bfin_read_DMC0_EMR1()); + printf("\tDDR_CTL: 0x%08x DDR_STAT: 0x%08x\n", + bfin_read_DMC0_CTL(), bfin_read_DMC0_STAT()); + printf("\tDDR_DLLCTL:0x%08x\n", bfin_read_DMC0_DLLCTL()); #endif #endif /* CONFIG_BLACKFIN */ diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h index c847069..c7cb834 100644 --- a/include/configs/bf609-ezkit.h +++ b/include/configs/bf609-ezkit.h @@ -64,6 +64,7 @@ #define CONFIG_BFIN_GET_SCLK (CONFIG_PLL_CLK/CONFIG_SYSCLK_DIV) #define CONFIG_BFIN_GET_SCLK0 (get_sclk()/CONFIG_SCLK0_DIV) #define CONFIG_BFIN_GET_SCLK1 (get_sclk()/CONFIG_SCLK1_DIV) +#define CONFIG_BFIN_GET_DCLK (get_cclk()/CONFIG_DCLK_DIV) /* * Memory Settings
Add system0, system1, dclk and cgu print info for Bf60x. Signed-off-by: Bob Liu <lliubbo@gmail.com> --- arch/blackfin/lib/board.c | 6 ++++++ arch/blackfin/lib/clocks.c | 10 +++++++++- common/cmd_reginfo.c | 17 +++++++++++++++++ include/configs/bf609-ezkit.h | 1 + 4 files changed, 33 insertions(+), 1 deletion(-)