Patchwork [U-Boot,v2] arm: rmobile: Add support for ATMARK-TECHNO Armadillo-800EVA board

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Submitter Nobuhiro Iwamatsu
Date Aug. 5, 2012, 10:35 p.m.
Message ID <1344206157-20257-1-git-send-email-nobuhiro.iwamatsu.yj@renesas.com>
Download mbox | patch
Permalink /patch/175214/
State Accepted
Delegated to: Albert ARIBAUD
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Comments

Nobuhiro Iwamatsu - Aug. 5, 2012, 10:35 p.m.
From: Hideyuki Sano <hideyuki.sano.dn@renesas.com>

The Armadillo-800EVA board has Renesas R-Mobile R8A7740, 512MB DDR3-SDRAM,
Ethernet, and more.

This patch supports the following functions:
 - 512MB DDR3-SDRAM
 - Serial console (SCIF)
 - Ethernet MAC(MII) & PHY(SMSC)

Signed-off-by: Hideyuki Sano <hideyuki.sano.dn@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
---
 v2: Fix typo in changelog

 MAINTAINERS                                        |    4 +
 arch/arm/include/asm/mach-types.h                  |    1 +
 board/atmark-techno/armadillo-800eva/Makefile      |   46 +++
 .../armadillo-800eva/armadillo-800eva.c            |  331 ++++++++++++++++++++
 boards.cfg                                         |    1 +
 include/configs/armadillo-800eva.h                 |  157 ++++++++++
 6 files changed, 540 insertions(+)
 create mode 100644 board/atmark-techno/armadillo-800eva/Makefile
 create mode 100644 board/atmark-techno/armadillo-800eva/armadillo-800eva.c
 create mode 100644 include/configs/armadillo-800eva.h

Patch

diff --git a/MAINTAINERS b/MAINTAINERS
index 564fe6a..6c58bdd 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -968,6 +968,10 @@  Tetsuyuki Kobayashi <koba@kmckk.co.jp>
 
 	kzm9g	SH73A0 (RMOBILE SoC)
 
+Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+
+	armadillo-800eva	R8A7740 (RMOBILE SoC)
+
 -------------------------------------------------------------------------
 
 Unknown / orphaned boards:
diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h
index 98c992c..529b3d5 100644
--- a/arch/arm/include/asm/mach-types.h
+++ b/arch/arm/include/asm/mach-types.h
@@ -1105,6 +1105,7 @@  extern unsigned int __machine_arch_type;
 #define MACH_TYPE_UBISYS_P9D_EVP       3493
 #define MACH_TYPE_ATDGP318             3494
 #define MACH_TYPE_OMAP5_SEVM           3777
+#define MACH_TYPE_ARMADILLO_800EVA     3863
 
 #define MACH_TYPE_KZM9G                4140
 
diff --git a/board/atmark-techno/armadillo-800eva/Makefile b/board/atmark-techno/armadillo-800eva/Makefile
new file mode 100644
index 0000000..9f9618b
--- /dev/null
+++ b/board/atmark-techno/armadillo-800eva/Makefile
@@ -0,0 +1,46 @@ 
+#
+# Copyright (C) 2012  Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= armadillo-800eva.o
+COBJS   := $(COBJS-y)
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
+
diff --git a/board/atmark-techno/armadillo-800eva/armadillo-800eva.c b/board/atmark-techno/armadillo-800eva/armadillo-800eva.c
new file mode 100644
index 0000000..2f91666
--- /dev/null
+++ b/board/atmark-techno/armadillo-800eva/armadillo-800eva.c
@@ -0,0 +1,331 @@ 
+/*
+ * Copyright (C) 2012  Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+
+#define s_init_wait(cnt) \
+		({	\
+			volatile u32 i = 0x10000 * cnt;	\
+			while (i > 0)	\
+				i--;	\
+		})
+
+#define USBCR1 0xE605810A
+
+void s_init(void)
+{
+	struct r8a7740_rwdt *rwdt0 = (struct r8a7740_rwdt *)RWDT0_BASE;
+	struct r8a7740_rwdt *rwdt1 = (struct r8a7740_rwdt *)RWDT1_BASE;
+	struct r8a7740_cpg *cpg = (struct r8a7740_cpg *)CPG_BASE;
+	struct r8a7740_bsc *bsc = (struct r8a7740_bsc *)BSC_BASE;
+	struct r8a7740_ddrp *ddrp = (struct r8a7740_ddrp *)DDRP_BASE;
+	struct r8a7740_dbsc *dbsc = (struct r8a7740_dbsc *)DBSC_BASE;
+
+	/* Watchdog init */
+	writew(0xA500, &rwdt0->rwtcsra0);
+	writew(0xA500, &rwdt1->rwtcsra0);
+
+	/* CPG */
+	writel(0xFF800080, &cpg->rmstpcr4);
+	writel(0xFF800080, &cpg->smstpcr4);
+
+	/* USB clock */
+	writel(0x00000080, &cpg->usbckcr);
+	s_init_wait(1);
+
+	/* USBCR1 */
+	writew(0x0710, USBCR1);
+
+	/* FRQCR */
+	writel(0x00000000, &cpg->frqcrb);
+	writel(0x62030533, &cpg->frqcra);
+	writel(0x208A354E, &cpg->frqcrc);
+	writel(0x80331050, &cpg->frqcrb);
+	s_init_wait(1);
+
+	writel(0x00000000, &cpg->frqcrd);
+	s_init_wait(1);
+
+	/* SUBClk */
+	writel(0x0000010B, &cpg->subckcr);
+
+	/* PLL */
+	writel(0x00004004, &cpg->pllc01cr);
+	s_init_wait(1);
+
+	writel(0xa0000000, &cpg->pllc2cr);
+	s_init_wait(2);
+
+	/* BSC */
+	writel(0x0000001B, &bsc->cmncr);
+
+	writel(0x20000000, &dbsc->dbcmd);
+	writel(0x10009C40, &dbsc->dbcmd);
+	s_init_wait(1);
+
+	writel(0x00000007, &dbsc->dbkind);
+	writel(0x0E030A02, &dbsc->dbconf0);
+	writel(0x00000001, &dbsc->dbphytype);
+	writel(0x00000000, &dbsc->dbbl);
+	writel(0x00000006, &dbsc->dbtr0);
+	writel(0x00000005, &dbsc->dbtr1);
+	writel(0x00000000, &dbsc->dbtr2);
+	writel(0x00000006, &dbsc->dbtr3);
+	writel(0x00080006, &dbsc->dbtr4);
+	writel(0x00000015, &dbsc->dbtr5);
+	writel(0x0000000f, &dbsc->dbtr6);
+	writel(0x00000004, &dbsc->dbtr7);
+	writel(0x00000018, &dbsc->dbtr8);
+	writel(0x00000006, &dbsc->dbtr9);
+	writel(0x00000006, &dbsc->dbtr10);
+	writel(0x0000000F, &dbsc->dbtr11);
+	writel(0x0000000D, &dbsc->dbtr12);
+	writel(0x000000A0, &dbsc->dbtr13);
+	writel(0x000A0003, &dbsc->dbtr14);
+	writel(0x00000003, &dbsc->dbtr15);
+	writel(0x40005005, &dbsc->dbtr16);
+	writel(0x0C0C0000, &dbsc->dbtr17);
+	writel(0x00000200, &dbsc->dbtr18);
+	writel(0x00000040, &dbsc->dbtr19);
+	writel(0x00000001, &dbsc->dbrnk0);
+	writel(0x00000110, &dbsc->dbdficnt);
+	writel(0x00000101, &ddrp->funcctrl);
+	writel(0x00000001, &ddrp->dllctrl);
+	writel(0x00000186, &ddrp->zqcalctrl);
+	writel(0xB3440051, &ddrp->zqodtctrl);
+	writel(0x94449443, &ddrp->rdctrl);
+	writel(0x000000C0, &ddrp->rdtmg);
+	writel(0x00000101, &ddrp->fifoinit);
+	writel(0x02060506, &ddrp->outctrl);
+	writel(0x00004646, &ddrp->dqcalofs1);
+	writel(0x00004646, &ddrp->dqcalofs2);
+	writel(0x800000aa, &ddrp->dqcalexp);
+	writel(0x00000000, &ddrp->dllctrl);
+	writel(0x00000000, DDRPNCNT);
+
+	writel(0x0000000C, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x00000002, DDRPNCNT);
+
+	writel(0x0000000C, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x00000187, &ddrp->zqcalctrl);
+
+	writel(0x00009C40, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x00009C40, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x00000010, &dbsc->dbdficnt);
+	writel(0x02060507, &ddrp->outctrl);
+
+	writel(0x00009C40, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x21009C40, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x00009C40, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x00009C40, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x00009C40, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x00009C40, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x11000044, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x2A000000, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x2B000000, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+
+	writel(0x29000004, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+
+	writel(0x28001520, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x03000200, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x000001FF, &dbsc->dbrfcnf0);
+	writel(0x00010C30, &dbsc->dbrfcnf1);
+	writel(0x00000000, &dbsc->dbrfcnf2);
+
+	writel(0x00000001, &dbsc->dbrfen);
+	writel(0x00000001, &dbsc->dbacen);
+
+	/* BSC */
+	writel(0x00410400, &bsc->cs0bcr);
+	writel(0x00410400, &bsc->cs2bcr);
+	writel(0x00410400, &bsc->cs5bbcr);
+	writel(0x02CB0400, &bsc->cs6abcr);
+
+	writel(0x00000440, &bsc->cs0wcr);
+	writel(0x00000440, &bsc->cs2wcr);
+	writel(0x00000240, &bsc->cs5bwcr);
+	writel(0x00000240, &bsc->cs6awcr);
+
+	writel(0x00000005, &bsc->rbwtcnt);
+	writel(0x00000002, &bsc->cs0wcr2);
+	writel(0x00000002, &bsc->cs2wcr2);
+	writel(0x00000002, &bsc->cs4wcr2);
+}
+
+#define GPIO_ICCR (0xE60581A0)
+#define ICCR_15BIT (1 << 15) /* any time 1 */
+#define IIC0_CONTA (1 << 7)
+#define IIC0_CONTB (1 << 6)
+#define IIC1_CONTA (1 << 5)
+#define IIC1_CONTB (1 << 4)
+#define IIC0_PS33E (1 << 1)
+#define IIC1_PS33E (1 << 0)
+#define GPIO_ICCR_DATA	\
+		(ICCR_15BIT |	\
+		IIC0_CONTA | IIC0_CONTB | IIC1_CONTA |	\
+		IIC1_CONTB | IIC0_PS33E | IIC1_PS33E)
+
+#define MSTPCR1         0xE6150134
+#define TMU0_MSTP125    (1 << 25)
+#define I2C0_MSTP116    (1 << 16)
+
+#define MSTPCR3         0xE615013C
+#define I2C1_MSTP323    (1 << 23)
+#define GETHER_MSTP309	(1 << 9)
+
+int board_early_init_f(void)
+{
+	/* TMU */
+	clrbits_le32(MSTPCR1, TMU0_MSTP125);
+
+	/* GETHER */
+	clrbits_le32(MSTPCR3, GETHER_MSTP309);
+
+	/* I2C 0/1 */
+	clrbits_le32(MSTPCR1, I2C0_MSTP116);
+	clrbits_le32(MSTPCR3, I2C1_MSTP323);
+
+	/* SCIFA1 */
+	r8a7740_pinmux_init();
+	gpio_request(GPIO_FN_SCIFA1_RXD, NULL);
+	gpio_request(GPIO_FN_SCIFA1_TXD, NULL);
+
+	/* IICCR */
+	writew(GPIO_ICCR_DATA, GPIO_ICCR);
+
+	return 0;
+}
+
+DECLARE_GLOBAL_DATA_PTR;
+int board_init(void)
+{
+	/* board id for linux */
+	gd->bd->bi_arch_number = MACH_TYPE_ARMADILLO_800EVA;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = ARMADILLO_800EVA_SDRAM_BASE + 0x100;
+
+	/* Init PFC controller */
+	r8a7740_pinmux_init();
+
+	/* GETHER Enable */
+	gpio_request(GPIO_FN_ET_CRS, NULL);
+	gpio_request(GPIO_FN_ET_MDC, NULL);
+	gpio_request(GPIO_FN_ET_MDIO, NULL);
+	gpio_request(GPIO_FN_ET_TX_ER, NULL);
+	gpio_request(GPIO_FN_ET_RX_ER, NULL);
+	gpio_request(GPIO_FN_ET_ERXD0, NULL);
+	gpio_request(GPIO_FN_ET_ERXD1, NULL);
+	gpio_request(GPIO_FN_ET_ERXD2, NULL);
+	gpio_request(GPIO_FN_ET_ERXD3, NULL);
+	gpio_request(GPIO_FN_ET_TX_CLK, NULL);
+	gpio_request(GPIO_FN_ET_TX_EN, NULL);
+	gpio_request(GPIO_FN_ET_ETXD0, NULL);
+	gpio_request(GPIO_FN_ET_ETXD1, NULL);
+	gpio_request(GPIO_FN_ET_ETXD2, NULL);
+	gpio_request(GPIO_FN_ET_ETXD3, NULL);
+	gpio_request(GPIO_FN_ET_PHY_INT, NULL);
+	gpio_request(GPIO_FN_ET_COL, NULL);
+	gpio_request(GPIO_FN_ET_RX_DV, NULL);
+	gpio_request(GPIO_FN_ET_RX_CLK, NULL);
+
+	gpio_request(GPIO_PORT18, NULL); /* PHY_RST */
+	gpio_direction_output(GPIO_PORT18, 1);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return sh_eth_initialize(bis);
+}
+
+const struct rmobile_sysinfo sysinfo = {
+	CONFIG_RMOBILE_BOARD_STRING
+};
+
+int board_late_init(void)
+{
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+}
diff --git a/boards.cfg b/boards.cfg
index 3c550b0..b260c1a 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -260,6 +260,7 @@  ventana                      arm         armv7       ventana             nvidia
 whistler                     arm         armv7       whistler            nvidia         tegra2
 u8500_href                   arm         armv7       u8500               st-ericsson    u8500
 kzm9g                        arm         armv7       kzm9g               kmc        	rmobile
+armadillo-800eva             arm         armv7       armadillo-800eva    atmark-techno  rmobile
 actux1_4_16                  arm         ixp         actux1              -              -           actux1:FLASH2X2
 actux1_4_32                  arm         ixp         actux1              -              -           actux1:FLASH2X2,RAM_32MB
 actux1_8_16                  arm         ixp         actux1              -              -           actux1:FLASH1X8
diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h
new file mode 100644
index 0000000..2f75099
--- /dev/null
+++ b/include/configs/armadillo-800eva.h
@@ -0,0 +1,157 @@ 
+/*
+ * Configuation settings for the bonito board
+ *
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ARMADILLO_800EVA_H
+#define __ARMADILLO_800EVA_H
+
+#undef DEBUG
+#define CONFIG_ARMV7
+#define CONFIG_R8A7740
+#define CONFIG_RMOBILE
+#define CONFIG_RMOBILE_BOARD_STRING "Armadillo-800EVA Board\n"
+#define CONFIG_SH_GPIO_PFC
+
+#include <asm/arch/rmobile.h>
+
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define BOARD_LATE_INIT
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS		""
+
+#define CONFIG_VERSION_VARIABLE
+#undef	CONFIG_SHOW_BOOT_PROGRESS
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define	CONFIG_SYS_NO_L2CACHE
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_USE_ARCH_MEMSET
+#define CONFIG_USE_ARCH_MEMCPY
+#define CONFIG_TMU_TIMER
+#define CONFIG_SYS_DCACHE_OFF
+
+/* STACK */
+#define CONFIG_SYS_INIT_SP_ADDR		0xE8083000
+#define STACK_AREA_SIZE				0xC000
+#define LOW_LEVEL_MERAM_STACK	\
+		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
+
+/* MEMORY */
+#define ARMADILLO_800EVA_SDRAM_BASE	0x40000000
+#define ARMADILLO_800EVA_SDRAM_SIZE	(512 * 1024 * 1024)
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT		"=> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_PBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		512
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE
+#define CONFIG_CONS_SCIF1
+#define SCIF0_BASE		0xe6c40000
+#define SCIF1_BASE		0xe6c50000
+#define SCIF2_BASE		0xe6c60000
+#define SCIF4_BASE		0xe6c80000
+#define	CONFIG_SCIF_A
+#undef	CONFIG_SYS_CONSOLE_INFO_QUIET
+#undef	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef	CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+#define CONFIG_SYS_MEMTEST_START	(ARMADILLO_800EVA_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
+					 504 * 1024 * 1024)
+#undef	CONFIG_SYS_ALT_MEMTEST
+#undef	CONFIG_SYS_MEMTEST_SCRATCH
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#define CONFIG_SYS_SDRAM_BASE		(ARMADILLO_800EVA_SDRAM_BASE)
+#define CONFIG_SYS_SDRAM_SIZE		(ARMADILLO_800EVA_SDRAM_SIZE)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + \
+					 64 * 1024 * 1024)
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_SYS_MONITOR_BASE		0x00000000
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1 * 1024 * 1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	(256)
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
+#define CONFIG_SYS_TEXT_BASE	0xE80C0000
+
+/* FLASH */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_BASE		0x00000000
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ (CONFIG_SYS_FLASH_BASE) }
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	3000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	3000
+#define CONFIG_SYS_FLASH_LOCK_TOUT	3000
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	3000
+
+/* ENV setting */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE	1
+#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + \
+				 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR)
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
+
+/* SH Ether */
+#define	CONFIG_NET_MULTI
+#define CONFIG_SH_ETHER
+#define CONFIG_SH_ETHER_USE_PORT	0
+#define CONFIG_SH_ETHER_PHY_ADDR	0x0
+#define CONFIG_SH_ETHER_BASE_ADDR	0xe9a00000
+#define CONFIG_SH_ETHER_SH7734_MII	(0x01)
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ	50000000
+#define CONFIG_SYS_TMU_CLK_DIV	4
+#define CONFIG_SYS_HZ		1000
+
+#endif	/* __ARMADILLO_800EVA_H */