From patchwork Thu Aug 2 16:04:10 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 174779 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id C57C62C008C for ; Fri, 3 Aug 2012 02:05:55 +1000 (EST) Received: from localhost ([::1]:37348 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SwxuL-00065J-RM for incoming@patchwork.ozlabs.org; Thu, 02 Aug 2012 12:05:53 -0400 Received: from eggs.gnu.org ([208.118.235.92]:39495) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SwxtP-0004dk-P1 for qemu-devel@nongnu.org; Thu, 02 Aug 2012 12:05:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SwxtH-0001xZ-Jb for qemu-devel@nongnu.org; Thu, 02 Aug 2012 12:04:55 -0400 Received: from mail-gh0-f173.google.com ([209.85.160.173]:37819) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SwxtH-0001u8-F9 for qemu-devel@nongnu.org; Thu, 02 Aug 2012 12:04:47 -0400 Received: by mail-gh0-f173.google.com with SMTP id r14so8584277ghr.4 for ; Thu, 02 Aug 2012 09:04:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=YjZPF+P/ZDCp03TBp7KPzacKqija9Ke1QDPmv9QizLs=; b=vGhlbiwafrKKDtHStaBAR9cdX1X5g6FIJXGLHBe9tptLepVjrfdjfLf4Vl7YyK+fGl ejm0VzMs6T+ZwMPzNxqwllF5SOc4rQhjMSSbHD+LUoKi05soswLw6DUDxEXdLJskidXD tkujJ/HMLAEPso+QT76bax7kk8tE44NndcuL/yhppRCkl2p9hLnjVAmbir9j6QgwGDFa mfYqm4U5AvWmMZ9myDZ8izBqjrw3oaB9DRMeFmLbd8LLumspBpLWsTEZ6wNE/dswfmPQ UZqU9/9w99/W+lOPrIB51GaER1y4oRvpjiYzashEggzVlosTghPNsjAq+C8hUD7LkCQW RtqQ== Received: by 10.43.46.194 with SMTP id up2mr4731874icb.22.1343923487033; Thu, 02 Aug 2012 09:04:47 -0700 (PDT) Received: from yakj.usersys.redhat.com (93-34-169-1.ip50.fastwebnet.it. [93.34.169.1]) by mx.google.com with ESMTPS id wm7sm13332071igb.6.2012.08.02.09.04.44 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 02 Aug 2012 09:04:46 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Thu, 2 Aug 2012 18:04:10 +0200 Message-Id: <1343923453-13026-8-git-send-email-pbonzini@redhat.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1343923453-13026-1-git-send-email-pbonzini@redhat.com> References: <1343923453-13026-1-git-send-email-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.173 Cc: yang.z.zhang@intel.com, aliguori@linux.vnet.ibm.com, mdroth@linux.vnet.ibm.com, quintela@redhat.com Subject: [Qemu-devel] [PATCH v3 07/10] RTC: Add divider reset support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Yang Zhang The first update cycle begins one-half seconds after divider reset is removed. This feature is useful for testing. Signed-off-by: Yang Zhang Signed-off-by: Paolo Bonzini --- hw/mc146818rtc.c | 50 +++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 41 insertions(+), 9 deletions(-) diff --git a/hw/mc146818rtc.c b/hw/mc146818rtc.c index 54c98a5..cb65c4f 100644 --- a/hw/mc146818rtc.c +++ b/hw/mc146818rtc.c @@ -83,6 +83,12 @@ static void rtc_update_time(RTCState *s); static void rtc_set_cmos(RTCState *s); static inline int rtc_from_bcd(RTCState *s, int a); +static inline bool rtc_running(RTCState *s) +{ + return (!(s->cmos_data[RTC_REG_B] & REG_B_SET) && + (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20); +} + static uint64_t get_guest_rtc_ns(RTCState *s) { uint64_t guest_rtc; @@ -199,11 +205,15 @@ static void check_update_timer(RTCState *s) uint64_t next_update_time; uint64_t guest_nsec; - /* From the data sheet: setting the SET bit does not prevent - * interrupts from occurring! However, it will prevent an - * alarm interrupt from occurring, because the time of day is - * not updated. + /* From the data sheet: "Holding the dividers in reset prevents + * interrupts from operating, while setting the SET bit allows" + * them to occur. However, it will prevent an alarm interrupt + * from occurring, because the time of day is not updated. */ + if ((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) { + qemu_del_timer(s->update_timer); + return; + } if ((s->cmos_data[RTC_REG_C] & REG_C_UF) && (s->cmos_data[RTC_REG_B] & REG_B_SET)) { qemu_del_timer(s->update_timer); @@ -268,6 +278,8 @@ static void rtc_update_timer(void *opaque) int32_t irqs = REG_C_UF; int32_t new_irqs; + assert((s->cmos_data[RTC_REG_A] & 0x60) != 0x60); + /* UIP might have been latched, update time and clear it. */ rtc_update_time(s); s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; @@ -312,12 +324,31 @@ static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data) case RTC_YEAR: s->cmos_data[s->cmos_index] = data; /* if in set mode, do not update the time */ - if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) { + if (rtc_running(s)) { rtc_set_time(s); check_update_timer(s); } break; case RTC_REG_A: + if ((data & 0x60) == 0x60) { + if (rtc_running(s)) { + rtc_update_time(s); + } + /* What happens to UIP when divider reset is enabled is + * unclear from the datasheet. Shouldn't matter much + * though. + */ + s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; + } else if (((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) && + (data & 0x70) <= 0x20) { + /* when the divider reset is removed, the first update cycle + * begins one-half second later*/ + if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) { + s->offset = 500000000; + rtc_set_time(s); + } + s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; + } /* UIP bit is read only */ s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) | (s->cmos_data[RTC_REG_A] & REG_A_UIP); @@ -327,7 +358,7 @@ static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data) case RTC_REG_B: if (data & REG_B_SET) { /* update cmos to when the rtc was stopping */ - if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) { + if (rtc_running(s)) { rtc_update_time(s); } /* set mode: reset UIP mode */ @@ -335,7 +366,8 @@ static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data) data &= ~REG_B_UIE; } else { /* if disabling set mode, update the time */ - if (s->cmos_data[RTC_REG_B] & REG_B_SET) { + if ((s->cmos_data[RTC_REG_B] & REG_B_SET) && + (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20) { s->offset = get_guest_rtc_ns(s) % NSEC_PER_SEC; rtc_set_time(s); } @@ -449,7 +481,7 @@ static int update_in_progress(RTCState *s) { int64_t guest_nsec; - if (s->cmos_data[RTC_REG_B] & REG_B_SET) { + if (!rtc_running(s)) { return 0; } if (qemu_timer_pending(s->update_timer)) { @@ -486,7 +518,7 @@ static uint32_t cmos_ioport_read(void *opaque, uint32_t addr) case RTC_YEAR: /* if not in set mode, calibrate cmos before * reading*/ - if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) { + if (rtc_running(s)) { rtc_update_time(s); } ret = s->cmos_data[s->cmos_index];