Patchwork [v3,14/32] PCI/tile: use PCIe capabilities access functions to simplify implementation

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Submitter Jiang Liu
Date Aug. 1, 2012, 3:54 p.m.
Message ID <1343836477-7287-15-git-send-email-jiang.liu@huawei.com>
Download mbox | patch
Permalink /patch/174502/
State Changes Requested
Headers show

Comments

Jiang Liu - Aug. 1, 2012, 3:54 p.m.
From: Jiang Liu <jiang.liu@huawei.com>

Use PCIe capabilities access functions to simplify PCIe tile implementation.

Signed-off-by: Jiang Liu <liuj97@gmail.com>
---
 arch/tile/kernel/pci.c |   25 +++++--------------------
 1 file changed, 5 insertions(+), 20 deletions(-)
Chris Metcalf - Aug. 1, 2012, 9:07 p.m.
On 8/1/2012 11:54 AM, Jiang Liu wrote:
> From: Jiang Liu <jiang.liu@huawei.com>
>
> Use PCIe capabilities access functions to simplify PCIe tile implementation.
>
> Signed-off-by: Jiang Liu <liuj97@gmail.com>
> ---
>  arch/tile/kernel/pci.c |   25 +++++--------------------
>  1 file changed, 5 insertions(+), 20 deletions(-)

Acked-by: Chris Metcalf <cmetcalf@tilera.com>

Patch

diff --git a/arch/tile/kernel/pci.c b/arch/tile/kernel/pci.c
index 0fdd99d..4640690 100644
--- a/arch/tile/kernel/pci.c
+++ b/arch/tile/kernel/pci.c
@@ -246,16 +246,13 @@  static void __devinit fixup_read_and_payload_sizes(void)
 
 	/* Scan for the smallest maximum payload size. */
 	while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
-		int pcie_caps_offset;
 		u32 devcap;
 		int max_payload;
 
-		pcie_caps_offset = pci_find_capability(dev, PCI_CAP_ID_EXP);
-		if (pcie_caps_offset == 0)
+		if (!pci_is_pcie(dev))
 			continue;
 
-		pci_read_config_dword(dev, pcie_caps_offset + PCI_EXP_DEVCAP,
-				      &devcap);
+		pci_pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &devcap);
 		max_payload = devcap & PCI_EXP_DEVCAP_PAYLOAD;
 		if (max_payload < smallest_max_payload)
 			smallest_max_payload = max_payload;
@@ -263,21 +260,9 @@  static void __devinit fixup_read_and_payload_sizes(void)
 
 	/* Now, set the max_payload_size for all devices to that value. */
 	new_values = (max_read_size << 12) | (smallest_max_payload << 5);
-	while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
-		int pcie_caps_offset;
-		u16 devctl;
-
-		pcie_caps_offset = pci_find_capability(dev, PCI_CAP_ID_EXP);
-		if (pcie_caps_offset == 0)
-			continue;
-
-		pci_read_config_word(dev, pcie_caps_offset + PCI_EXP_DEVCTL,
-				     &devctl);
-		devctl &= ~(PCI_EXP_DEVCTL_PAYLOAD | PCI_EXP_DEVCTL_READRQ);
-		devctl |= new_values;
-		pci_write_config_word(dev, pcie_caps_offset + PCI_EXP_DEVCTL,
-				      devctl);
-	}
+	while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL)
+		pci_pcie_capability_change_word(dev, PCI_EXP_DEVCTL, new_values,
+				PCI_EXP_DEVCTL_PAYLOAD | PCI_EXP_DEVCTL_READRQ);
 }