Patchwork [v3,24/32] PCI/ath9k: use PCIe capabilities access functions to simplify implementation

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Submitter Jiang Liu
Date Aug. 1, 2012, 3:54 p.m.
Message ID <1343836477-7287-25-git-send-email-jiang.liu@huawei.com>
Download mbox | patch
Permalink /patch/174493/
State Changes Requested
Headers show

Comments

Jiang Liu - Aug. 1, 2012, 3:54 p.m.
From: Jiang Liu <jiang.liu@huawei.com>

Use PCIe capabilities access functions to simplify ath9k driver's
implementation.

Signed-off-by: Jiang Liu <liuj97@gmail.com>
---
 drivers/net/wireless/ath/ath9k/pci.c |   21 ++++++---------------
 1 file changed, 6 insertions(+), 15 deletions(-)

Patch

diff --git a/drivers/net/wireless/ath/ath9k/pci.c b/drivers/net/wireless/ath/ath9k/pci.c
index a856b51..1aff99c 100644
--- a/drivers/net/wireless/ath/ath9k/pci.c
+++ b/drivers/net/wireless/ath/ath9k/pci.c
@@ -112,12 +112,7 @@  static void ath_pci_aspm_init(struct ath_common *common)
 	struct ath_hw *ah = sc->sc_ah;
 	struct pci_dev *pdev = to_pci_dev(sc->dev);
 	struct pci_dev *parent;
-	int pos;
-	u8 aspm;
-
-	pos = pci_pcie_cap(pdev);
-	if (!pos)
-		return;
+	u16 aspm;
 
 	parent = pdev->bus->self;
 	if (!parent)
@@ -125,24 +120,20 @@  static void ath_pci_aspm_init(struct ath_common *common)
 
 	if (ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) {
 		/* Bluetooth coexistance requires disabling ASPM. */
-		pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &aspm);
-		aspm &= ~(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
-		pci_write_config_byte(pdev, pos + PCI_EXP_LNKCTL, aspm);
+		pci_pcie_capability_change_word(pdev, PCI_EXP_LNKCTL,
+			0, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
 
 		/*
 		 * Both upstream and downstream PCIe components should
 		 * have the same ASPM settings.
 		 */
-		pos = pci_pcie_cap(parent);
-		pci_read_config_byte(parent, pos + PCI_EXP_LNKCTL, &aspm);
-		aspm &= ~(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
-		pci_write_config_byte(parent, pos + PCI_EXP_LNKCTL, aspm);
+		pci_pcie_capability_change_word(parent, PCI_EXP_LNKCTL,
+			0, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
 
 		return;
 	}
 
-	pos = pci_pcie_cap(parent);
-	pci_read_config_byte(parent, pos +  PCI_EXP_LNKCTL, &aspm);
+	pci_pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &aspm);
 	if (aspm & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) {
 		ah->aspm_enabled = true;
 		/* Initialize PCIe PM and SERDES registers. */