From patchwork Wed Aug 1 15:54:06 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiang Liu X-Patchwork-Id: 174480 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id A52F62C0083 for ; Thu, 2 Aug 2012 01:55:31 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755776Ab2HAPzK (ORCPT ); Wed, 1 Aug 2012 11:55:10 -0400 Received: from mail-gg0-f174.google.com ([209.85.161.174]:52606 "EHLO mail-gg0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755767Ab2HAPzH (ORCPT ); Wed, 1 Aug 2012 11:55:07 -0400 Received: by ggnl2 with SMTP id l2so175463ggn.19 for ; Wed, 01 Aug 2012 08:55:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=2r1eJ3qad+LxaYNSavg7scm8lYtT8/pJEhGyvSCFcZU=; b=OOjPGAUHveVAHYtWsf0XR9IQQmahr/vQ3hThzL8NKnnn9ldp/ukDeTN3P9CjiGPo7i x+gwfdMWQgplSF5/Njtcu3PyiiR26sTJQ7rhFPtCAaQJ6VRVxIo3LyRARnICE9MT9uJj MXJHO1BUJm62XROaoYoLS2qb1woA7ASYprFFwW65jepVQdtpDk+jN/1ZS0UN9H6Z0FWA 1EcoVkZyOgUK0NjoIYB7Oy7hAURhUFJaI+Nwwq6K9e0wVG9cAd8b169Ter64SDR/joxG VzzuAcc8RLIbqIuIpBHK7r6n5Cqe8W8SvTiVBGCntomIg+gRR+UQAhQ59T9F9jdKmOv6 Y8hw== Received: by 10.66.73.6 with SMTP id h6mr11565460pav.27.1343836506790; Wed, 01 Aug 2012 08:55:06 -0700 (PDT) Received: from localhost.localdomain ([58.250.81.2]) by mx.google.com with ESMTPS id pe8sm2816231pbc.76.2012.08.01.08.54.59 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 01 Aug 2012 08:55:05 -0700 (PDT) From: Jiang Liu To: Bjorn Helgaas , Don Dutile Cc: Yijing Wang , Yinghai Lu , Taku Izumi , "Rafael J . Wysocki" , Kenji Kaneshige , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Jiang Liu Subject: [PATCH v3 01/32] PCI: add pcie_flags_reg into struct pci_dev to cache PCIe capabilities register Date: Wed, 1 Aug 2012 23:54:06 +0800 Message-Id: <1343836477-7287-2-git-send-email-jiang.liu@huawei.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1343836477-7287-1-git-send-email-jiang.liu@huawei.com> References: <1343836477-7287-1-git-send-email-jiang.liu@huawei.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Yijing Wang From: Yijing Wang Since PCI Express Capabilities Register is read only, cache its value into struct pci_dev to avoid repeatedly calling pci_read_config_*(). Signed-off-by: Yijing Wang Signed-off-by: Jiang Liu --- drivers/pci/probe.c | 3 ++- include/linux/pci.h | 10 ++++++++++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 6c143b4..ba4d855 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -929,7 +929,8 @@ void set_pcie_port_type(struct pci_dev *pdev) pdev->is_pcie = 1; pdev->pcie_cap = pos; pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); - pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4; + pdev->pcie_flags_reg = reg16; + pdev->pcie_type = pci_pcie_type(pdev); pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; } diff --git a/include/linux/pci.h b/include/linux/pci.h index 5faa831..95662b2 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -258,6 +258,7 @@ struct pci_dev { u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */ u8 rom_base_reg; /* which config register controls the ROM */ u8 pin; /* which interrupt pin this device uses */ + u16 pcie_flags_reg; /* cached PCI-E Capabilities Register */ struct pci_driver *driver; /* which driver has allocated this device */ u64 dma_mask; /* Mask of the bits of bus address this @@ -1650,6 +1651,15 @@ static inline bool pci_is_pcie(struct pci_dev *dev) return !!pci_pcie_cap(dev); } +/** + * pci_pcie_type - get the PCIe device/port type + * @dev: PCI device + */ +static inline int pci_pcie_type(const struct pci_dev *dev) +{ + return (dev->pcie_flags_reg & PCI_EXP_FLAGS_TYPE) >> 4; +} + void pci_request_acs(void); bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); bool pci_acs_path_enabled(struct pci_dev *start,