Patchwork [U-Boot,3/5] am33xx: Add support for TI AM335x StarterKit EVM

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Submitter Tom Rini
Date July 31, 2012, 9:07 p.m.
Message ID <1343768849-18521-4-git-send-email-trini@ti.com>
Download mbox | patch
Permalink /patch/174333/
State Accepted
Commit 65d750be590db1ad3f045f45a8fbac59c4ccb9b5
Delegated to: Tom Rini
Headers show

Comments

Tom Rini - July 31, 2012, 9:07 p.m.
- Board requires gpio0 #7 to be set to power DDR3.
- Board uses DDR3, add a way to determine which DDR type to call
  config_ddr with.
- Both of the above require filling in the header structure early, move
  it into the data section.

Signed-off-by: Tom Rini <trini@ti.com>
---
 arch/arm/cpu/armv7/am33xx/board.c             |   41 +++++++++++++++++++++++--
 arch/arm/include/asm/arch-am33xx/common_def.h |    1 +
 board/ti/am335x/mux.c                         |   10 ++++++
 3 files changed, 50 insertions(+), 2 deletions(-)

Patch

diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 4634a9a..a1fe104 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -29,6 +29,7 @@ 
 #include <asm/io.h>
 #include <asm/omap_common.h>
 #include <asm/emif.h>
+#include <asm/gpio.h>
 #include <i2c.h>
 #include <miiphy.h>
 #include <cpsw.h>
@@ -52,6 +53,9 @@  const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
 #define MII_MODE_ENABLE		0x0
 #define RGMII_MODE_ENABLE	0xA
 
+/* GPIO that controls power to DDR on EVM-SK */
+#define GPIO_DDR_VTT_EN		7
+
 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 
 /*
@@ -72,13 +76,18 @@  struct am335x_baseboard_id {
 	char mac_addr[NO_OF_MAC_ADDR][ETH_ALEN];
 };
 
-static struct am335x_baseboard_id header;
+static struct am335x_baseboard_id __attribute__((section (".data"))) header;
 
 static inline int board_is_bone(void)
 {
 	return !strncmp(header.name, "A335BONE", NAME_LEN);
 }
 
+static inline int board_is_evm_sk(void)
+{
+	return !strncmp("A335X_SK", header.name, NAME_LEN);
+}
+
 /*
  * Read header information from EEPROM into global structure.
  */
@@ -145,6 +154,18 @@  static void init_timer(void)
 #endif
 
 /*
+ * Determine what type of DDR we have.
+ */
+static short inline board_memory_type(void)
+{
+	/* The following boards are known to use DDR3. */
+	if (board_is_evm_sk())
+		return EMIF_REG_SDRAM_TYPE_DDR3;
+
+	return EMIF_REG_SDRAM_TYPE_DDR2;
+}
+
+/*
  * early system init of muxing and clocks.
  */
 void s_init(void)
@@ -185,7 +206,23 @@  void s_init(void)
 
 	preloader_console_init();
 
-	config_ddr(EMIF_REG_SDRAM_TYPE_DDR2);
+	/* Initalize the board header */
+	enable_i2c0_pin_mux();
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	if (read_eeprom() < 0)
+		puts("Could not get board ID.\n");
+
+	if (board_is_evm_sk()) {
+		/*
+		 * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
+		 * This is safe enough to do on older revs.
+		 */
+		enable_gpio0_7_pin_mux();
+		gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
+		gpio_direction_output(GPIO_DDR_VTT_EN, 1);
+	}
+
+	config_ddr(board_memory_type());
 #endif
 
 	/* Enable MMC0 */
diff --git a/arch/arm/include/asm/arch-am33xx/common_def.h b/arch/arm/include/asm/arch-am33xx/common_def.h
index 5a7b0f3..1fe6258 100644
--- a/arch/arm/include/asm/arch-am33xx/common_def.h
+++ b/arch/arm/include/asm/arch-am33xx/common_def.h
@@ -18,6 +18,7 @@ 
 
 extern void enable_uart0_pin_mux(void);
 extern void enable_mmc0_pin_mux(void);
+extern void enable_gpio0_7_pin_mux(void);
 extern void enable_i2c0_pin_mux(void);
 extern void enable_mii1_pin_mux(void);
 extern void enable_rgmii1_pin_mux(void);
diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
index a1661e6..9907d96 100644
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@@ -288,6 +288,11 @@  static struct module_pin_mux i2c1_pin_mux[] = {
 	{-1},
 };
 
+static struct module_pin_mux gpio0_7_pin_mux[] = {
+	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)},	/* GPIO0_7 */
+	{-1},
+};
+
 static struct module_pin_mux rgmii1_pin_mux[] = {
 	{OFFSET(mii1_txen), MODE(2)},			/* RGMII1_TCTL */
 	{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE},	/* RGMII1_RCTL */
@@ -370,3 +375,8 @@  void enable_mii1_pin_mux(void)
 {
 	configure_module_pin_mux(mii1_pin_mux);
 }
+
+void enable_gpio0_7_pin_mux(void)
+{
+	configure_module_pin_mux(gpio0_7_pin_mux);
+}