From patchwork Tue Jul 31 18:59:29 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 174312 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id DC3662C0302 for ; Wed, 1 Aug 2012 05:01:35 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 61E2028101; Tue, 31 Jul 2012 21:00:59 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id wzB+MGSLhuP5; Tue, 31 Jul 2012 21:00:59 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DE6D928102; Tue, 31 Jul 2012 21:00:08 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 67D13280E4 for ; Tue, 31 Jul 2012 20:59:58 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id GQI5-vgX5-I1 for ; Tue, 31 Jul 2012 20:59:57 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pb0-f44.google.com (mail-pb0-f44.google.com [209.85.160.44]) by theia.denx.de (Postfix) with ESMTPS id B229A280CD for ; Tue, 31 Jul 2012 20:59:54 +0200 (CEST) Received: by mail-pb0-f44.google.com with SMTP id jt11so755244pbb.3 for ; Tue, 31 Jul 2012 11:59:54 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=J9xvYP9UrbAtiewKnAGVIp2MrPyJK1eB8OTC8IGyxVY=; b=jk/b7xcWeqy96/ESeQvfy7LOXWRZmRy4SkYbHYbn1aZWAoKp0ZiGq1yIQcmjUPAdk7 izOOSpgKhr1EhL720u7WuPRvifyLs81TQUB6q8RgvULsTYNljNF5mU1e1HGj6RiDAg/4 xrHri+rQLuWiqtK1kY+LkJt5lVIj8BkYA9jckC4ZPcSLo7wU8H5eslnSHRpNGQfwwlvy 2q8F473G9WNiGUpCkRSUUjLZr7BqRgh4Ob2RCdP7V6ZXplbSA8SOCyp2rvR74oP/y8yZ bAp/gbp9vXzFRfPVyOrwwnA7oXKWpAsPC+HpIO7yushH7G0KU/yaGEeQL1+B5/giNoIi f8ZA== Received: by 10.68.220.39 with SMTP id pt7mr46836748pbc.40.1343761194003; Tue, 31 Jul 2012 11:59:54 -0700 (PDT) Received: from localhost.localdomain (S0106002369de4dac.cg.shawcable.net. [70.73.24.112]) by mx.google.com with ESMTPS id ot4sm806366pbb.65.2012.07.31.11.59.52 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 31 Jul 2012 11:59:53 -0700 (PDT) From: mathieu.poirier@linaro.org To: u-boot@lists.denx.de Date: Tue, 31 Jul 2012 12:59:29 -0600 Message-Id: <1343761173-1135-8-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1343761173-1135-1-git-send-email-mathieu.poirier@linaro.org> References: <1343761173-1135-1-git-send-email-mathieu.poirier@linaro.org> X-Gm-Message-State: ALoCoQkijAg2pJv8WfLCq5mMzAqc5KRGuR4yhIIxu+kto1I92CP1yOIjTQt0vlIV8oUs1WrP0Gg2 Subject: [U-Boot] [PATCH 07/11] u8500: Moving processor-specific functions to cpu area. X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: "Mathieu J. Poirier" Functions such as providing power to the MMC device and reading the processor version register should be in the cpu area for access by multiple u8500-based boards. Signed-off-by: Mathieu Poirier Signed-off-by: John Rigby --- arch/arm/cpu/armv7/u8500/cpu.c | 86 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-u8500/sys_proto.h | 1 + board/st-ericsson/u8500/u8500_href.c | 75 +----------------------- 3 files changed, 88 insertions(+), 74 deletions(-) diff --git a/arch/arm/cpu/armv7/u8500/cpu.c b/arch/arm/cpu/armv7/u8500/cpu.c index fece201..593199c 100644 --- a/arch/arm/cpu/armv7/u8500/cpu.c +++ b/arch/arm/cpu/armv7/u8500/cpu.c @@ -28,6 +28,30 @@ #include #include #include +#include + +#include + +#define CPUID_DB8500V1 0x411fc091 +#define CPUID_DB8500V2 0x412fc091 +#define ASICID_DB8500V11 0x008500A1 + +static unsigned int read_asicid(void) +{ + unsigned int *address = (void *)U8500_BOOTROM_BASE + + U8500_BOOTROM_ASIC_ID_OFFSET; + return readl(address); +} + +static int cpu_is_u8500v11(void) +{ + return read_asicid() == ASICID_DB8500V11; +} + +static int cpu_is_u8500v2(void) +{ + return read_cpuid() == CPUID_DB8500V2; +} #ifdef CONFIG_ARCH_CPU_INIT /* @@ -41,3 +65,65 @@ int arch_cpu_init(void) return 0; } #endif /* CONFIG_ARCH_CPU_INIT */ + +#ifdef CONFIG_MMC + +#define LDO_VAUX3_MASK 0x3 +#define LDO_VAUX3_ENABLE 0x1 +#define VAUX3_VOLTAGE_2_9V 0xd + +#define AB8500_REGU_CTRL2 0x4 +#define AB8500_REGU_VRF1VAUX3_REGU_REG 0x040A +#define AB8500_REGU_VRF1VAUX3_SEL_REG 0x0421 + +int u8500_mmc_power_init(void) +{ + int ret; + int val; + + if (!cpu_is_u8500v11()) + return 0; + + /* + * On v1.1 HREF boards (HREF+), Vaux3 needs to be enabled for the SD + * card to work. This is done by enabling the regulators in the AB8500 + * via PRCMU I2C transactions. + * + * This code is derived from the handling of AB8500_LDO_VAUX3 in + * ab8500_ldo_enable() and ab8500_ldo_disable() in Linux. + * + * Turn off and delay is required to have it work across soft reboots. + */ + + ret = prcmu_i2c_read(AB8500_REGU_CTRL2, AB8500_REGU_VRF1VAUX3_REGU_REG); + if (ret < 0) + goto out; + + val = ret; + + /* Turn off */ + ret = prcmu_i2c_write(AB8500_REGU_CTRL2, AB8500_REGU_VRF1VAUX3_REGU_REG, + val & ~LDO_VAUX3_MASK); + if (ret < 0) + goto out; + + udelay(10 * 1000); + + /* Set the voltage to 2.9V */ + ret = prcmu_i2c_write(AB8500_REGU_CTRL2, + AB8500_REGU_VRF1VAUX3_SEL_REG, + VAUX3_VOLTAGE_2_9V); + if (ret < 0) + goto out; + + val = val & ~LDO_VAUX3_MASK; + val = val | LDO_VAUX3_ENABLE; + + /* Turn on the supply */ + ret = prcmu_i2c_write(AB8500_REGU_CTRL2, + AB8500_REGU_VRF1VAUX3_REGU_REG, val); + +out: + return ret; +} +#endif /* CONFIG_MMC */ diff --git a/arch/arm/include/asm/arch-u8500/sys_proto.h b/arch/arm/include/asm/arch-u8500/sys_proto.h index bac5e79..a8ef9e5 100644 --- a/arch/arm/include/asm/arch-u8500/sys_proto.h +++ b/arch/arm/include/asm/arch-u8500/sys_proto.h @@ -23,5 +23,6 @@ #define _SYS_PROTO_H_ void gpio_init(void); +int u8500_mmc_power_init(void); #endif /* _SYS_PROTO_H_ */ diff --git a/board/st-ericsson/u8500/u8500_href.c b/board/st-ericsson/u8500/u8500_href.c index fe72684..e75f8b4 100644 --- a/board/st-ericsson/u8500/u8500_href.c +++ b/board/st-ericsson/u8500/u8500_href.c @@ -139,18 +139,6 @@ void show_boot_progress(int progress) } #endif -static unsigned int read_asicid(void) -{ - unsigned int *address = (void *)U8500_BOOTROM_BASE - + U8500_BOOTROM_ASIC_ID_OFFSET; - return readl(address); -} - -int cpu_is_u8500v11(void) -{ - return read_asicid() == 0x008500A1; -} - /* * Miscellaneous platform dependent initialisations */ @@ -227,67 +215,6 @@ unsigned int addr_vall_arr[] = { }; #ifdef CONFIG_BOARD_LATE_INIT -#ifdef CONFIG_MMC - -#define LDO_VAUX3_MASK 0x3 -#define LDO_VAUX3_ENABLE 0x1 -#define VAUX3_VOLTAGE_2_9V 0xd - -#define AB8500_REGU_CTRL2 0x4 -#define AB8500_REGU_VRF1VAUX3_REGU_REG 0x040A -#define AB8500_REGU_VRF1VAUX3_SEL_REG 0x0421 - -static int hrefplus_mmc_power_init(void) -{ - int ret; - int val; - - if (!cpu_is_u8500v11()) - return 0; - - /* - * On v1.1 HREF boards (HREF+), Vaux3 needs to be enabled for the SD - * card to work. This is done by enabling the regulators in the AB8500 - * via PRCMU I2C transactions. - * - * This code is derived from the handling of AB8500_LDO_VAUX3 in - * ab8500_ldo_enable() and ab8500_ldo_disable() in Linux. - * - * Turn off and delay is required to have it work across soft reboots. - */ - - ret = prcmu_i2c_read(AB8500_REGU_CTRL2, AB8500_REGU_VRF1VAUX3_REGU_REG); - if (ret < 0) - goto out; - - val = ret; - - /* Turn off */ - ret = prcmu_i2c_write(AB8500_REGU_CTRL2, AB8500_REGU_VRF1VAUX3_REGU_REG, - val & ~LDO_VAUX3_MASK); - if (ret < 0) - goto out; - - udelay(10 * 1000); - - /* Set the voltage to 2.9V */ - ret = prcmu_i2c_write(AB8500_REGU_CTRL2, - AB8500_REGU_VRF1VAUX3_SEL_REG, - VAUX3_VOLTAGE_2_9V); - if (ret < 0) - goto out; - - val = val & ~LDO_VAUX3_MASK; - val = val | LDO_VAUX3_ENABLE; - - /* Turn on the supply */ - ret = prcmu_i2c_write(AB8500_REGU_CTRL2, - AB8500_REGU_VRF1VAUX3_REGU_REG, val); - -out: - return ret; -} -#endif /* * called after all initialisation were done, but before the generic * mmc_initialize(). @@ -314,7 +241,7 @@ int board_late_init(void) setenv("board_id", "1"); } #ifdef CONFIG_MMC - hrefplus_mmc_power_init(); + u8500_mmc_power_init(); /* * config extended GPIO pins for level shifter and