Patchwork [U-Boot,04/17] am33xx: Convert to using <asm/emif.h> to describe the EMIF

login
register
mail settings
Submitter Tom Rini
Date July 30, 2012, 4:48 p.m.
Message ID <1343666943-25378-5-git-send-email-trini@ti.com>
Download mbox | patch
Permalink /patch/174050/
State Accepted
Commit 7d5eb34908d3a7318d1a3f4afb2c926066a2befc
Delegated to: Tom Rini
Headers show

Comments

Tom Rini - July 30, 2012, 4:48 p.m.
Signed-off-by: Tom Rini <trini@ti.com>
---
 arch/arm/cpu/armv7/am33xx/ddr.c             |   29 ++++++++++++++-------------
 arch/arm/include/asm/arch-am33xx/ddr_defs.h |   27 -------------------------
 2 files changed, 15 insertions(+), 41 deletions(-)

Patch

diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index ed982c1..e592609 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -18,12 +18,13 @@  http://www.ti.com/
 #include <asm/arch/cpu.h>
 #include <asm/arch/ddr_defs.h>
 #include <asm/io.h>
+#include <asm/emif.h>
 
 /**
  * Base address for EMIF instances
  */
-static struct emif_regs *emif_reg = {
-				(struct emif_regs *)EMIF4_0_CFG_BASE};
+static struct emif_reg_struct *emif_reg = {
+				(struct emif_reg_struct *)EMIF4_0_CFG_BASE};
 
 /**
  * Base address for DDR instance
@@ -48,10 +49,10 @@  static struct ddr_cmdtctrl *ioctrl_reg = {
  */
 int config_sdram(struct sdram_config *cfg)
 {
-	writel(cfg->sdrcr, &emif_reg->sdrcr);
-	writel(cfg->sdrcr2, &emif_reg->sdrcr2);
-	writel(cfg->refresh, &emif_reg->sdrrcr);
-	writel(cfg->refresh_sh, &emif_reg->sdrrcsr);
+	writel(cfg->sdrcr, &emif_reg->emif_sdram_config);
+	writel(cfg->sdrcr2, &emif_reg->emif_lpddr2_nvm_config);
+	writel(cfg->refresh, &emif_reg->emif_sdram_ref_ctrl);
+	writel(cfg->refresh_sh, &emif_reg->emif_sdram_ref_ctrl_shdw);
 
 	return 0;
 }
@@ -61,12 +62,12 @@  int config_sdram(struct sdram_config *cfg)
  */
 int set_sdram_timings(struct sdram_timing *t)
 {
-	writel(t->time1, &emif_reg->sdrtim1);
-	writel(t->time1_sh, &emif_reg->sdrtim1sr);
-	writel(t->time2, &emif_reg->sdrtim2);
-	writel(t->time2_sh, &emif_reg->sdrtim2sr);
-	writel(t->time3, &emif_reg->sdrtim3);
-	writel(t->time3_sh, &emif_reg->sdrtim3sr);
+	writel(t->time1, &emif_reg->emif_sdram_tim_1);
+	writel(t->time1_sh, &emif_reg->emif_sdram_tim_1_shdw);
+	writel(t->time2, &emif_reg->emif_sdram_tim_2);
+	writel(t->time2_sh, &emif_reg->emif_sdram_tim_2_shdw);
+	writel(t->time3, &emif_reg->emif_sdram_tim_3);
+	writel(t->time3_sh, &emif_reg->emif_sdram_tim_3_shdw);
 
 	return 0;
 }
@@ -76,8 +77,8 @@  int set_sdram_timings(struct sdram_timing *t)
  */
 int config_ddr_phy(struct ddr_phy_control *p)
 {
-	writel(p->reg, &emif_reg->ddrphycr);
-	writel(p->reg_sh, &emif_reg->ddrphycsr);
+	writel(p->reg, &emif_reg->emif_ddr_phy_ctrl_1);
+	writel(p->reg_sh, &emif_reg->emif_ddr_phy_ctrl_1_shdw);
 
 	return 0;
 }
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 388336f..c62f826 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -56,33 +56,6 @@ 
 #define DDR_IOCTRL_VALUE	0x18B
 
 /**
- * This structure represents the EMIF registers on AM33XX devices.
- */
-struct emif_regs {
-	unsigned int sdrrev;		/* offset 0x00 */
-	unsigned int sdrstat;		/* offset 0x04 */
-	unsigned int sdrcr;		/* offset 0x08 */
-	unsigned int sdrcr2;		/* offset 0x0C */
-	unsigned int sdrrcr;		/* offset 0x10 */
-	unsigned int sdrrcsr;		/* offset 0x14 */
-	unsigned int sdrtim1;		/* offset 0x18 */
-	unsigned int sdrtim1sr;		/* offset 0x1C */
-	unsigned int sdrtim2;		/* offset 0x20 */
-	unsigned int sdrtim2sr;		/* offset 0x24 */
-	unsigned int sdrtim3;		/* offset 0x28 */
-	unsigned int sdrtim3sr;		/* offset 0x2C */
-	unsigned int res1[2];
-	unsigned int sdrmcr;		/* offset 0x38 */
-	unsigned int sdrmcsr;		/* offset 0x3C */
-	unsigned int res2[8];
-	unsigned int sdritr;		/* offset 0x60 */
-	unsigned int res3[32];
-	unsigned int ddrphycr;		/* offset 0xE4 */
-	unsigned int ddrphycsr;		/* offset 0xE8 */
-	unsigned int ddrphycr2;		/* offset 0xEC */
-};
-
-/**
  * Encapsulates DDR PHY control and corresponding shadow registers.
  */
 struct ddr_phy_control {