| Message ID | 1343665815-25606-3-git-send-email-lwithers@guralp.com |
|---|---|
| State | Changes Requested |
| Delegated to: | Tom Rini |
| Headers | show |
On Mon, Jul 30, 2012 at 04:30:15PM +0000, Laurence Withers wrote: > Replace a magic number for the DDR2/mDDR PHY clock ID with a proper > definition. In addition, don't request this clock ID on DA830 hardware, > which does not have a DDR2/mDDR PHY (or associated PLL controller). > > Signed-off-by: Laurence Withers <lwithers@guralp.com> > Cc: Prabhakar Lad <prabhakar.csengg@gmail.com> > --- > arch/arm/cpu/arm926ejs/davinci/cpu.c | 3 ++- > arch/arm/include/asm/arch-davinci/hardware.h | 2 ++ > 2 files changed, 4 insertions(+), 1 deletions(-) > > diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c > index 4bdb08b..b31add8 100644 > --- a/arch/arm/cpu/arm926ejs/davinci/cpu.c > +++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c > @@ -122,7 +122,8 @@ int set_cpu_clk_info(void) > { > gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000; > /* DDR PHY uses an x2 input clock */ > - gd->bd->bi_ddr_freq = clk_get(0x10001) / 1000000; > + gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 : > + (clk_get(DAVINCI_DDR_CLKID) / 1000000); > gd->bd->bi_dsp_freq = 0; > return 0; > } > diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h > index 0fce940..7f3dcc2 100644 > --- a/arch/arm/include/asm/arch-davinci/hardware.h > +++ b/arch/arm/include/asm/arch-davinci/hardware.h > @@ -459,10 +459,12 @@ enum davinci_clk_ids { > DAVINCI_PLL0_SYSCLK2 = DAVINCI_PLLC0_FLAG | 2, > DAVINCI_PLL0_SYSCLK4 = DAVINCI_PLLC0_FLAG | 4, > DAVINCI_PLL0_SYSCLK6 = DAVINCI_PLLC0_FLAG | 6, > + DAVINCI_PLL1_SYSCLK1 = DAVINCI_PLLC1_FLAG | 1, > DAVINCI_PLL1_SYSCLK2 = DAVINCI_PLLC1_FLAG | 2, > > /* map peripherals to clock IDs */ > DAVINCI_ARM_CLKID = DAVINCI_PLL0_SYSCLK6, > + DAVINCI_DDR_CLKID = DAVINCI_PLL1_SYSCLK1, > DAVINCI_MDIO_CLKID = DAVINCI_PLL0_SYSCLK4, > DAVINCI_MMC_CLKID = DAVINCI_PLL0_SYSCLK2, > DAVINCI_SPI0_CLKID = DAVINCI_PLL0_SYSCLK2, > -- > 1.7.2.5 > Hi, This patch does depend on my earlier patch to tidy up the definition of set_cpu_clk_info() : http://lists.denx.de/pipermail/u-boot/2012-July/129205.html Bye for now,
On Mon, Jul 30, 2012 at 04:34:39PM +0000, Laurence Withers wrote: > On Mon, Jul 30, 2012 at 04:30:15PM +0000, Laurence Withers wrote: > > Replace a magic number for the DDR2/mDDR PHY clock ID with a proper > > definition. In addition, don't request this clock ID on DA830 hardware, > > which does not have a DDR2/mDDR PHY (or associated PLL controller). > > > > Signed-off-by: Laurence Withers <lwithers@guralp.com> > > Cc: Prabhakar Lad <prabhakar.csengg@gmail.com> > > --- > > arch/arm/cpu/arm926ejs/davinci/cpu.c | 3 ++- > > arch/arm/include/asm/arch-davinci/hardware.h | 2 ++ > > 2 files changed, 4 insertions(+), 1 deletions(-) > > > > diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c > > index 4bdb08b..b31add8 100644 > > --- a/arch/arm/cpu/arm926ejs/davinci/cpu.c > > +++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c > > @@ -122,7 +122,8 @@ int set_cpu_clk_info(void) > > { > > gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000; > > /* DDR PHY uses an x2 input clock */ > > - gd->bd->bi_ddr_freq = clk_get(0x10001) / 1000000; > > + gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 : > > + (clk_get(DAVINCI_DDR_CLKID) / 1000000); > > gd->bd->bi_dsp_freq = 0; > > return 0; > > } > > diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h > > index 0fce940..7f3dcc2 100644 > > --- a/arch/arm/include/asm/arch-davinci/hardware.h > > +++ b/arch/arm/include/asm/arch-davinci/hardware.h > > @@ -459,10 +459,12 @@ enum davinci_clk_ids { > > DAVINCI_PLL0_SYSCLK2 = DAVINCI_PLLC0_FLAG | 2, > > DAVINCI_PLL0_SYSCLK4 = DAVINCI_PLLC0_FLAG | 4, > > DAVINCI_PLL0_SYSCLK6 = DAVINCI_PLLC0_FLAG | 6, > > + DAVINCI_PLL1_SYSCLK1 = DAVINCI_PLLC1_FLAG | 1, > > DAVINCI_PLL1_SYSCLK2 = DAVINCI_PLLC1_FLAG | 2, > > > > /* map peripherals to clock IDs */ > > DAVINCI_ARM_CLKID = DAVINCI_PLL0_SYSCLK6, > > + DAVINCI_DDR_CLKID = DAVINCI_PLL1_SYSCLK1, > > DAVINCI_MDIO_CLKID = DAVINCI_PLL0_SYSCLK4, > > DAVINCI_MMC_CLKID = DAVINCI_PLL0_SYSCLK2, > > DAVINCI_SPI0_CLKID = DAVINCI_PLL0_SYSCLK2, > > -- > > 1.7.2.5 > > > > Hi, > > This patch does depend on my earlier patch to tidy up the definition of > set_cpu_clk_info() : > > http://lists.denx.de/pipermail/u-boot/2012-July/129205.html Can you please post everything as a series of 4 patches so that we don't add and then replace the magic value with the enum? Other than that, I'm happy with the series and will apply the updated series on Friday or so, thanks!
diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c index 4bdb08b..b31add8 100644 --- a/arch/arm/cpu/arm926ejs/davinci/cpu.c +++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c @@ -122,7 +122,8 @@ int set_cpu_clk_info(void) { gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000; /* DDR PHY uses an x2 input clock */ - gd->bd->bi_ddr_freq = clk_get(0x10001) / 1000000; + gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 : + (clk_get(DAVINCI_DDR_CLKID) / 1000000); gd->bd->bi_dsp_freq = 0; return 0; } diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index 0fce940..7f3dcc2 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -459,10 +459,12 @@ enum davinci_clk_ids { DAVINCI_PLL0_SYSCLK2 = DAVINCI_PLLC0_FLAG | 2, DAVINCI_PLL0_SYSCLK4 = DAVINCI_PLLC0_FLAG | 4, DAVINCI_PLL0_SYSCLK6 = DAVINCI_PLLC0_FLAG | 6, + DAVINCI_PLL1_SYSCLK1 = DAVINCI_PLLC1_FLAG | 1, DAVINCI_PLL1_SYSCLK2 = DAVINCI_PLLC1_FLAG | 2, /* map peripherals to clock IDs */ DAVINCI_ARM_CLKID = DAVINCI_PLL0_SYSCLK6, + DAVINCI_DDR_CLKID = DAVINCI_PLL1_SYSCLK1, DAVINCI_MDIO_CLKID = DAVINCI_PLL0_SYSCLK4, DAVINCI_MMC_CLKID = DAVINCI_PLL0_SYSCLK2, DAVINCI_SPI0_CLKID = DAVINCI_PLL0_SYSCLK2,
Replace a magic number for the DDR2/mDDR PHY clock ID with a proper definition. In addition, don't request this clock ID on DA830 hardware, which does not have a DDR2/mDDR PHY (or associated PLL controller). Signed-off-by: Laurence Withers <lwithers@guralp.com> Cc: Prabhakar Lad <prabhakar.csengg@gmail.com> --- arch/arm/cpu/arm926ejs/davinci/cpu.c | 3 ++- arch/arm/include/asm/arch-davinci/hardware.h | 2 ++ 2 files changed, 4 insertions(+), 1 deletions(-)