diff --git a/gcc/common/config/rs6000/rs6000-common.c b/gcc/common/config/rs6000/rs6000-common.c
index f40b69e..407e1cc 100644
--- a/gcc/common/config/rs6000/rs6000-common.c
+++ b/gcc/common/config/rs6000/rs6000-common.c
@@ -1,7 +1,5 @@
 /* Common hooks for IBM RS/6000.
-   Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-   2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
-   Free Software Foundation, Inc.
+   Copyright (C) 1991-2012 Free Software Foundation, Inc.
 
    This file is part of GCC.
 
@@ -83,12 +81,6 @@ rs6000_handle_option (struct gcc_options *opts, struct gcc_options *opts_set,
 
   switch (code)
     {
-    case OPT_mno_power:
-      opts->x_target_flags &= ~(MASK_POWER | MASK_POWER2
-				| MASK_MULTIPLE | MASK_STRING);
-      opts_set->x_target_flags |= (MASK_POWER | MASK_POWER2
-				   | MASK_MULTIPLE | MASK_STRING);
-      break;
     case OPT_mno_powerpc:
       opts->x_target_flags &= ~(MASK_POWERPC | MASK_PPC_GPOPT
 				| MASK_PPC_GFXOPT | MASK_POWERPC64);
@@ -143,24 +135,6 @@ rs6000_handle_option (struct gcc_options *opts, struct gcc_options *opts_set,
 	}
       break;
 
-    case OPT_mpower:
-      if (value == 1)
-	{
-	  opts->x_target_flags |= (MASK_MULTIPLE | MASK_STRING);
-	  opts_set->x_target_flags |= (MASK_MULTIPLE | MASK_STRING);
-	}
-      break;
-
-    case OPT_mpower2:
-      if (value == 1)
-	{
-	  opts->x_target_flags |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
-	  opts_set->x_target_flags |= (MASK_POWER
-				       | MASK_MULTIPLE
-				       | MASK_STRING);
-	}
-      break;
-
     case OPT_mpowerpc_gpopt:
     case OPT_mpowerpc_gfxopt:
       if (value == 1)
diff --git a/gcc/config/rs6000/aix43.h b/gcc/config/rs6000/aix43.h
index 8f5786f..9388dd0 100644
--- a/gcc/config/rs6000/aix43.h
+++ b/gcc/config/rs6000/aix43.h
@@ -22,14 +22,8 @@
 /* The macro SUBTARGET_OVERRIDE_OPTIONS is provided for subtargets, to
    get control in TARGET_OPTION_OVERRIDE.  */
 
-#define NON_POWERPC_MASKS (MASK_POWER | MASK_POWER2)
 #define SUBTARGET_OVERRIDE_OPTIONS					\
 do {									\
-  if (TARGET_64BIT && (target_flags & NON_POWERPC_MASKS))		\
-    {									\
-      target_flags &= ~NON_POWERPC_MASKS;				\
-      warning (0, "-maix64 and POWER architecture are incompatible");	\
-    }									\
   if (TARGET_64BIT && ! TARGET_POWERPC64)				\
     {									\
       target_flags |= MASK_POWERPC64;					\
@@ -55,14 +49,10 @@ do {									\
 #undef ASM_CPU_SPEC
 #define ASM_CPU_SPEC \
 "%{!mcpu*: %{!maix64: \
-  %{mpower: %{!mpower2: -mpwr}} \
-  %{mpower2: -mpwr2} \
   %{mpowerpc*: %{!mpowerpc64: -mppc}} \
   %{mpowerpc64: -mppc64} \
   %{!mpower*: %{!mpowerpc*: %(asm_default)}}}} \
 %{mcpu=common: -mcom} \
-%{mcpu=power: -mpwr} \
-%{mcpu=power2: -mpwr2} \
 %{mcpu=power3: -m620} \
 %{mcpu=power4: -m620} \
 %{mcpu=powerpc: -mppc} \
diff --git a/gcc/config/rs6000/aix51.h b/gcc/config/rs6000/aix51.h
index 00373ff..372e781 100644
--- a/gcc/config/rs6000/aix51.h
+++ b/gcc/config/rs6000/aix51.h
@@ -22,14 +22,8 @@
 /* The macro SUBTARGET_OVERRIDE_OPTIONS is provided for subtargets, to
    get control in TARGET_OPTION_OVERRIDE.  */
 
-#define NON_POWERPC_MASKS (MASK_POWER | MASK_POWER2)
 #define SUBTARGET_OVERRIDE_OPTIONS					\
 do {									\
-  if (TARGET_64BIT && (target_flags & NON_POWERPC_MASKS))		\
-    {									\
-      target_flags &= ~NON_POWERPC_MASKS;				\
-      warning (0, "-maix64 and POWER architecture are incompatible");	\
-    }									\
   if (TARGET_64BIT && ! TARGET_POWERPC64)				\
     {									\
       target_flags |= MASK_POWERPC64;					\
@@ -49,14 +43,10 @@ do {									\
 #undef ASM_CPU_SPEC
 #define ASM_CPU_SPEC \
 "%{!mcpu*: %{!maix64: \
-  %{mpower: %{!mpower2: -mpwr}} \
-  %{mpower2: -mpwr2} \
   %{mpowerpc*: %{!mpowerpc64: -mppc}} \
   %{mpowerpc64: -mppc64} \
   %{!mpower*: %{!mpowerpc*: %(asm_default)}}}} \
 %{mcpu=common: -mcom} \
-%{mcpu=power: -mpwr} \
-%{mcpu=power2: -mpwr2} \
 %{mcpu=power3: -m620} \
 %{mcpu=power4: -m620} \
 %{mcpu=powerpc: -mppc} \
diff --git a/gcc/config/rs6000/aix52.h b/gcc/config/rs6000/aix52.h
index c658571..206b9fe 100644
--- a/gcc/config/rs6000/aix52.h
+++ b/gcc/config/rs6000/aix52.h
@@ -1,7 +1,6 @@
 /* Definitions of target machine for GNU compiler,
    for IBM RS/6000 POWER running AIX V5.2.
-   Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
-   Free Software Foundation, Inc.
+   Copyright (C) 2002-2012 Free Software Foundation, Inc.
    Contributed by David Edelsohn (edelsohn@gnu.org).
 
    This file is part of GCC.
@@ -23,14 +22,8 @@
 /* The macro SUBTARGET_OVERRIDE_OPTIONS is provided for subtargets, to
    get control in TARGET_OPTION_OVERRIDE.  */
 
-#define NON_POWERPC_MASKS (MASK_POWER | MASK_POWER2)
 #define SUBTARGET_OVERRIDE_OPTIONS					\
 do {									\
-  if (TARGET_64BIT && (target_flags & NON_POWERPC_MASKS))		\
-    {									\
-      target_flags &= ~NON_POWERPC_MASKS;				\
-      warning (0, "-maix64 and POWER architecture are incompatible");	\
-    }									\
   if (TARGET_64BIT && ! TARGET_POWERPC64)				\
     {									\
       target_flags |= MASK_POWERPC64;					\
@@ -113,9 +106,6 @@ do {									\
 #undef  PROCESSOR_DEFAULT64
 #define PROCESSOR_DEFAULT64 PROCESSOR_POWER4
 
-#undef  TARGET_POWER
-#define TARGET_POWER 0
-
 /* AIX does not support Altivec.  */
 #undef  TARGET_ALTIVEC
 #define TARGET_ALTIVEC 0
diff --git a/gcc/config/rs6000/aix53.h b/gcc/config/rs6000/aix53.h
index 36af085..44ad5cf 100644
--- a/gcc/config/rs6000/aix53.h
+++ b/gcc/config/rs6000/aix53.h
@@ -1,7 +1,6 @@
 /* Definitions of target machine for GNU compiler,
    for IBM RS/6000 POWER running AIX V5.3.
-   Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
-   Free Software Foundation, Inc.
+   Copyright (C) 2002-2012 Free Software Foundation, Inc.
    Contributed by David Edelsohn (edelsohn@gnu.org).
 
    This file is part of GCC.
@@ -23,14 +22,8 @@
 /* The macro SUBTARGET_OVERRIDE_OPTIONS is provided for subtargets, to
    get control in TARGET_OPTION_OVERRIDE.  */
 
-#define NON_POWERPC_MASKS (MASK_POWER | MASK_POWER2)
 #define SUBTARGET_OVERRIDE_OPTIONS					\
 do {									\
-  if (TARGET_64BIT && (target_flags & NON_POWERPC_MASKS))		\
-    {									\
-      target_flags &= ~NON_POWERPC_MASKS;				\
-      warning (0, "-maix64 and POWER architecture are incompatible");	\
-    }									\
   if (TARGET_64BIT && ! TARGET_POWERPC64)				\
     {									\
       target_flags |= MASK_POWERPC64;					\
@@ -119,9 +112,6 @@ do {									\
 #undef  PROCESSOR_DEFAULT64
 #define PROCESSOR_DEFAULT64 PROCESSOR_POWER5
 
-#undef  TARGET_POWER
-#define TARGET_POWER 0
-
 /* Define this macro as a C expression for the initializer of an
    array of string to tell the driver program which options are
    defaults for this target and thus do not need to be handled
diff --git a/gcc/config/rs6000/aix61.h b/gcc/config/rs6000/aix61.h
index f04c712..1000e11 100644
--- a/gcc/config/rs6000/aix61.h
+++ b/gcc/config/rs6000/aix61.h
@@ -1,7 +1,6 @@
 /* Definitions of target machine for GNU compiler,
    for IBM RS/6000 POWER running AIX V6.1.
-   Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
-   Free Software Foundation, Inc.
+   Copyright (C) 2002-2012 Free Software Foundation, Inc.
    Contributed by David Edelsohn (edelsohn@gnu.org).
 
    This file is part of GCC.
@@ -23,14 +22,8 @@
 /* The macro SUBTARGET_OVERRIDE_OPTIONS is provided for subtargets, to
    get control in TARGET_OPTION_OVERRIDE.  */
 
-#define NON_POWERPC_MASKS (MASK_POWER | MASK_POWER2)
 #define SUBTARGET_OVERRIDE_OPTIONS					\
 do {									\
-  if (TARGET_64BIT && (target_flags & NON_POWERPC_MASKS))		\
-    {									\
-      target_flags &= ~NON_POWERPC_MASKS;				\
-      warning (0, "-maix64 and POWER architecture are incompatible");	\
-    }									\
   if (TARGET_64BIT && ! TARGET_POWERPC64)				\
     {									\
       target_flags |= MASK_POWERPC64;					\
@@ -120,9 +113,6 @@ do {									\
 #undef  PROCESSOR_DEFAULT64
 #define PROCESSOR_DEFAULT64 PROCESSOR_POWER7
 
-#undef  TARGET_POWER
-#define TARGET_POWER 0
-
 /* Define this macro as a C expression for the initializer of an
    array of string to tell the driver program which options are
    defaults for this target and thus do not need to be handled
diff --git a/gcc/config/rs6000/darwin.h b/gcc/config/rs6000/darwin.h
index 17aa184..92cd698 100644
--- a/gcc/config/rs6000/darwin.h
+++ b/gcc/config/rs6000/darwin.h
@@ -1,6 +1,5 @@
 /* Target definitions for PowerPC running Darwin (Mac OS X).
-   Copyright (C) 1997, 2000, 2001, 2003, 2004, 2005, 2006, 2007, 2008, 2010,
-   2011, 2012 Free Software Foundation, Inc.
+   Copyright (C) 1997-2012 Free Software Foundation, Inc.
    Contributed by Apple Computer Inc.
 
    This file is part of GCC.
@@ -285,8 +284,6 @@ extern int darwin_emit_branch_islands;
                       | MASK_PPC_GFXOPT)
 
 /* Darwin only runs on PowerPC, so short-circuit POWER patterns.  */
-#undef  TARGET_POWER
-#define TARGET_POWER 0
 #undef  TARGET_IEEEQUAD
 #define TARGET_IEEEQUAD 0
 
diff --git a/gcc/config/rs6000/driver-rs6000.c b/gcc/config/rs6000/driver-rs6000.c
index 178bb42..68b5257 100644
--- a/gcc/config/rs6000/driver-rs6000.c
+++ b/gcc/config/rs6000/driver-rs6000.c
@@ -373,8 +373,6 @@ static const struct asm_name asm_names[] = {
 #else
   { "common",	"-mcom" },
   { "cell",	"-mcell" },
-  { "power",	"-mpwr" },
-  { "power2",	"-mpwrx" },
   { "power3",	"-mppc64" },
   { "power4",	"-mpower4" },
   { "power5",	"%(asm_cpu_power5)" },
@@ -420,12 +418,9 @@ static const struct asm_name asm_names[] = {
   { "e300c3",	"-me300" },
   { "e500mc",	"-me500mc" },
   { NULL,	"\
-%{mpower: %{!mpower2: -mpwr}} \
-%{mpower2: -mpwrx} \
 %{mpowerpc64*: -mppc64} \
 %{!mpowerpc64*: %{mpowerpc*: -mppc}} \
-%{mno-power: %{!mpowerpc*: -mcom}} \
-%{!mno-power: %{!mpower*: %(asm_default)}}" },
+%{!mpowerpc*: -mcom}" },
 #endif
 };
 
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index 0717b91..c6d344d 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -1,6 +1,5 @@
-/* Subroutines for the C front end on the POWER and PowerPC architectures.
-   Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
-   Free Software Foundation, Inc.
+/* Subroutines for the C front end on the PowerPC architecture.
+   Copyright (C) 2002-2012 Free Software Foundation, Inc.
 
    Contributed by Zack Weinberg <zack@codesourcery.com>
    and Paolo Bonzini <bonzini@gnu.org>
@@ -294,10 +293,6 @@ rs6000_target_modify_macros (bool define_p, int flags, unsigned bu_mask)
 	     (unsigned) flags, bu_mask);
 
   /* target_flags based options.  */
-  if ((flags & MASK_POWER2) != 0)
-    rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR2");
-  else if ((flags & MASK_POWER) != 0)
-    rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR");
   if ((flags & MASK_POWERPC) != 0)
     rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC");
   if ((flags & MASK_PPC_GPOPT) != 0)
@@ -353,7 +348,7 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfile)
 
   /* _ARCH_COM does not fit in the framework of target_modify_macros, so handle
      it specially.  */
-  if (! TARGET_POWER && ! TARGET_POWER2 && ! TARGET_POWERPC)
+  if (! TARGET_POWERPC)
     builtin_define ("_ARCH_COM");
   if (TARGET_FRE)
     builtin_define ("__RECIP__");
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index 74c5803..5d76f6a 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -55,7 +55,7 @@ RS6000_CPU ("476fp", PROCESSOR_PPC476,
 	    | MASK_FPRND | MASK_CMPB | MASK_MULHW | MASK_DLMZB)
 RS6000_CPU ("505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK)
 RS6000_CPU ("601", PROCESSOR_PPC601,
-	    MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING)
+	    POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING)
 RS6000_CPU ("602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT)
 RS6000_CPU ("603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT)
 RS6000_CPU ("603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT)
@@ -102,9 +102,6 @@ RS6000_CPU ("G5", PROCESSOR_POWER4,
 	    POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
 RS6000_CPU ("titan", PROCESSOR_TITAN,
 	    POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB)
-RS6000_CPU ("power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING)
-RS6000_CPU ("power2", PROCESSOR_POWER,
-	    MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING)
 RS6000_CPU ("power3", PROCESSOR_PPC630,
 	    POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64)
 RS6000_CPU ("power4", PROCESSOR_POWER4,
diff --git a/gcc/config/rs6000/rs6000-tables.opt b/gcc/config/rs6000/rs6000-tables.opt
index 2cc5f7a..26e700f 100644
--- a/gcc/config/rs6000/rs6000-tables.opt
+++ b/gcc/config/rs6000/rs6000-tables.opt
@@ -159,38 +159,32 @@ EnumValue
 Enum(rs6000_cpu_opt_value) String(titan) Value(43)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(power) Value(44)
+Enum(rs6000_cpu_opt_value) String(power3) Value(44)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(power2) Value(45)
+Enum(rs6000_cpu_opt_value) String(power4) Value(45)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(power3) Value(46)
+Enum(rs6000_cpu_opt_value) String(power5) Value(46)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(power4) Value(47)
+Enum(rs6000_cpu_opt_value) String(power5+) Value(47)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(power5) Value(48)
+Enum(rs6000_cpu_opt_value) String(power6) Value(48)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(power5+) Value(49)
+Enum(rs6000_cpu_opt_value) String(power6x) Value(49)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(power6) Value(50)
+Enum(rs6000_cpu_opt_value) String(power7) Value(50)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(power6x) Value(51)
+Enum(rs6000_cpu_opt_value) String(powerpc) Value(51)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(power7) Value(52)
+Enum(rs6000_cpu_opt_value) String(powerpc64) Value(52)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(powerpc) Value(53)
-
-EnumValue
-Enum(rs6000_cpu_opt_value) String(powerpc64) Value(54)
-
-EnumValue
-Enum(rs6000_cpu_opt_value) String(rs64) Value(55)
+Enum(rs6000_cpu_opt_value) String(rs64) Value(53)
 
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 337a95d..1ed9155 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -1467,7 +1467,6 @@ enum {
    the user's specification.  */
 
 enum {
-  POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
   POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT | MASK_STRICT_ALIGN
 		   | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
 		   | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW
@@ -2417,7 +2416,7 @@ rs6000_option_override_internal (bool global_init_p)
       rs6000_pointer_size = 32;
     }
 
-  set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
+  set_masks = POWERPC_MASKS | MASK_SOFT_FLOAT;
 #ifdef OS_MISSING_POWERPC64
   if (OS_MISSING_POWERPC64)
     set_masks &= ~MASK_POWERPC64;
@@ -6525,10 +6524,9 @@ rs6000_conditional_register_usage (void)
   if (TARGET_DEBUG_TARGET)
     fprintf (stderr, "rs6000_conditional_register_usage called\n");
 
-  /* Set MQ register fixed (already call_used) if not POWER
-     architecture (PPC601) so that it will not be allocated.  */
-  if (! TARGET_POWER)
-    fixed_regs[64] = 1;
+  /* Set MQ register fixed (already call_used) so that it will not be
+     allocated.  */
+  fixed_regs[64] = 1;
 
   /* 64-bit AIX and Linux reserve GPR13 for thread-private data.  */
   if (TARGET_64BIT)
@@ -7200,17 +7198,6 @@ rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
 
     case TImode:
       rs6000_eliminate_indexed_memrefs (operands);
-
-      if (TARGET_POWER)
-	{
-	  emit_insn (gen_rtx_PARALLEL (VOIDmode,
-		       gen_rtvec (2,
-				  gen_rtx_SET (VOIDmode,
-					       operands[0], operands[1]),
-				  gen_rtx_CLOBBER (VOIDmode,
-						   gen_rtx_SCRATCH (SImode)))));
-	  return;
-	}
       break;
 
     default:
@@ -12624,8 +12611,7 @@ rs6000_common_init_builtins (void)
 static void
 rs6000_init_libfuncs (void)
 {
-  if (DEFAULT_ABI != ABI_V4 && TARGET_XCOFF
-      && !TARGET_POWER2 && !TARGET_POWERPC)
+  if (DEFAULT_ABI != ABI_V4 && TARGET_XCOFF && !TARGET_POWERPC)
     {
       /* AIX library routines for float->int conversion.  */
       set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
@@ -12682,7 +12668,7 @@ rs6000_init_libfuncs (void)
       set_optab_libfunc (neg_optab, TFmode, "_q_neg");
       set_optab_libfunc (smul_optab, TFmode, "_q_mul");
       set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
-      if (TARGET_PPC_GPOPT || TARGET_POWER2)
+      if (TARGET_PPC_GPOPT)
 	set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
 
       set_optab_libfunc (eq_optab, TFmode, "_q_feq");
@@ -20236,7 +20222,7 @@ rs6000_output_function_prologue (FILE *file,
     }
 
   /* Write .extern for AIX common mode routines, if needed.  */
-  if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
+  if (! TARGET_POWERPC && ! common_mode_defined)
     {
       fputs ("\t.extern __mulh\n", file);
       fputs ("\t.extern __mull\n", file);
@@ -22539,7 +22525,7 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
                scheduling pass will not know about this latency since
                the mtctr instruction, which has the latency associated
                to it, will be generated by reload.  */
-            return TARGET_POWER ? 5 : 4;
+            return 4;
           case TYPE_BRANCH:
             /* Leave some extra cycles between a compare and its
                dependent branch, to inhibit expensive mispredicts.  */
@@ -27351,8 +27337,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
 #ifdef MASK_STRICT_ALIGN
   { "strict-align",	MASK_STRICT_ALIGN,	false, false },
 #endif
-  { "power",		MASK_POWER,		false, false },
-  { "power2",		MASK_POWER2,		false, false },
   { "powerpc",		MASK_POWERPC,		false, false },
   { "soft-float",	MASK_SOFT_FLOAT,	false, false },
   { "string",		MASK_STRING,		false, false },
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index fea4bac..612d202 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -101,17 +101,12 @@
    you make changes here, make them also there.  */
 #define ASM_CPU_SPEC \
 "%{!mcpu*: \
-  %{mpower: %{!mpower2: -mpwr}} \
-  %{mpower2: -mpwrx} \
   %{mpowerpc64*: -mppc64} \
   %{!mpowerpc64*: %{mpowerpc*: -mppc}} \
-  %{mno-power: %{!mpowerpc*: -mcom}} \
-  %{!mno-power: %{!mpower*: %(asm_default)}}} \
+  %{!mpowerpc*: -mcom}} \
 %{mcpu=native: %(asm_cpu_native)} \
 %{mcpu=common: -mcom} \
 %{mcpu=cell: -mcell} \
-%{mcpu=power: -mpwr} \
-%{mcpu=power2: -mpwrx} \
 %{mcpu=power3: -mppc64} \
 %{mcpu=power4: -mpower4} \
 %{mcpu=power5: %(asm_cpu_power5)} \
@@ -332,7 +327,7 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
     /* The option machinery will define this.  */
 #endif
 
-#define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
+#define TARGET_DEFAULT (MASK_MULTIPLE | MASK_STRING)
 
 /* FPU operations supported. 
    Each use of TARGET_SINGLE_FLOAT or TARGET_DOUBLE_FLOAT must 
@@ -348,7 +343,6 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
 
 /* Define generic processor types based upon current deployment.  */
 #define PROCESSOR_COMMON    PROCESSOR_PPC601
-#define PROCESSOR_POWER     PROCESSOR_PPC601
 #define PROCESSOR_POWERPC   PROCESSOR_PPC604
 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
 
@@ -1877,8 +1871,7 @@ extern unsigned rs6000_pmode;
 
    The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
    have been dropped from the PowerPC architecture.  */
-
-#define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0)
+#define SHIFT_COUNT_TRUNCATED 0
 
 /* Adjust the length of an INSN.  LENGTH is the currently-computed length and
    should be adjusted to reflect any required changes.  This macro is used when
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 0dc4d34..166ec60 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -661,8 +661,6 @@ (define_expand "extendqisi2"
 {
   if (TARGET_POWERPC)
     emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
-  else if (TARGET_POWER)
-    emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
   else
     emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
   DONE;
@@ -727,20 +725,6 @@ (define_split
 		    (const_int 0)))]
   "")
 
-(define_expand "extendqisi2_power"
-  [(parallel [(set (match_dup 2)
-		   (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
-			      (const_int 24)))
-	      (clobber (scratch:SI))])
-   (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
-		   (ashiftrt:SI (match_dup 2)
-				(const_int 24)))
-	      (clobber (scratch:SI))])]
-  "TARGET_POWER"
-  "
-{ operands[1] = gen_lowpart (SImode, operands[1]);
-  operands[2] = gen_reg_rtx (SImode); }")
-
 (define_expand "extendqisi2_no_power"
   [(set (match_dup 2)
 	(ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
@@ -748,7 +732,7 @@ (define_expand "extendqisi2_no_power"
    (set (match_operand:SI 0 "gpc_reg_operand" "")
 	(ashiftrt:SI (match_dup 2)
 		     (const_int 24)))]
-  "! TARGET_POWER && ! TARGET_POWERPC"
+  "! TARGET_POWERPC"
   "
 { operands[1] = gen_lowpart (SImode, operands[1]);
   operands[2] = gen_reg_rtx (SImode); }")
@@ -828,8 +812,6 @@ (define_expand "extendqihi2"
 {
   if (TARGET_POWERPC)
     emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
-  else if (TARGET_POWER)
-    emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
   else
     emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
   DONE;
@@ -894,21 +876,6 @@ (define_split
 		    (const_int 0)))]
   "")
 
-(define_expand "extendqihi2_power"
-  [(parallel [(set (match_dup 2)
-		   (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
-			      (const_int 24)))
-	      (clobber (scratch:SI))])
-   (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
-		   (ashiftrt:SI (match_dup 2)
-				(const_int 24)))
-	      (clobber (scratch:SI))])]
-  "TARGET_POWER"
-  "
-{ operands[0] = gen_lowpart (SImode, operands[0]);
-  operands[1] = gen_lowpart (SImode, operands[1]);
-  operands[2] = gen_reg_rtx (SImode); }")
-
 (define_expand "extendqihi2_no_power"
   [(set (match_dup 2)
 	(ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
@@ -916,7 +883,7 @@ (define_expand "extendqihi2_no_power"
    (set (match_operand:HI 0 "gpc_reg_operand" "")
 	(ashiftrt:SI (match_dup 2)
 		     (const_int 24)))]
-  "! TARGET_POWER && ! TARGET_POWERPC"
+  "! TARGET_POWERPC"
   "
 { operands[0] = gen_lowpart (SImode, operands[0]);
   operands[1] = gen_lowpart (SImode, operands[1]);
@@ -1921,11 +1888,6 @@ (define_expand "sub<mode>3"
     }
 }")
 
-;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
-;; instruction and some auxiliary computations.  Then we just have a single
-;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
-;; combine.
-
 (define_expand "sminsi3"
   [(set (match_dup 3)
 	(if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
@@ -1934,32 +1896,14 @@ (define_expand "sminsi3"
 			 (minus:SI (match_dup 2) (match_dup 1))))
    (set (match_operand:SI 0 "gpc_reg_operand" "")
 	(minus:SI (match_dup 2) (match_dup 3)))]
-  "TARGET_POWER || TARGET_ISEL"
+  "TARGET_ISEL"
   "
 {
-  if (TARGET_ISEL)
-    {
-      operands[2] = force_reg (SImode, operands[2]);
-      rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
-      DONE;
-    }
-
-  operands[3] = gen_reg_rtx (SImode);
+  operands[2] = force_reg (SImode, operands[2]);
+  rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
+  DONE;
 }")
 
-(define_split
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
-		 (match_operand:SI 2 "reg_or_short_operand" "")))
-   (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
-  "TARGET_POWER"
-  [(set (match_dup 3)
-	(if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
-			 (const_int 0)
-			 (minus:SI (match_dup 2) (match_dup 1))))
-   (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
-  "")
-
 (define_expand "smaxsi3"
   [(set (match_dup 3)
 	(if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
@@ -1968,31 +1912,14 @@ (define_expand "smaxsi3"
 			 (minus:SI (match_dup 2) (match_dup 1))))
    (set (match_operand:SI 0 "gpc_reg_operand" "")
 	(plus:SI (match_dup 3) (match_dup 1)))]
-  "TARGET_POWER || TARGET_ISEL"
+  "TARGET_ISEL"
   "
 {
-  if (TARGET_ISEL)
-    {
-      operands[2] = force_reg (SImode, operands[2]);
-      rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
-      DONE;
-    }
-  operands[3] = gen_reg_rtx (SImode);
+  operands[2] = force_reg (SImode, operands[2]);
+  rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
+  DONE;
 }")
 
-(define_split
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
-		 (match_operand:SI 2 "reg_or_short_operand" "")))
-   (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
-  "TARGET_POWER"
-  [(set (match_dup 3)
-	(if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
-			 (const_int 0)
-			 (minus:SI (match_dup 2) (match_dup 1))))
-   (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
-  "")
-
 (define_expand "uminsi3"
   [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
 			      (match_dup 5)))
@@ -2003,17 +1930,11 @@ (define_expand "uminsi3"
 				       (minus:SI (match_dup 4) (match_dup 3))))
    (set (match_operand:SI 0 "gpc_reg_operand" "")
 	(minus:SI (match_dup 2) (match_dup 3)))]
-  "TARGET_POWER || TARGET_ISEL"
+  "TARGET_ISEL"
   "
 {
-  if (TARGET_ISEL)
-    {
-      rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
-      DONE;
-    }
-  operands[3] = gen_reg_rtx (SImode);
-  operands[4] = gen_reg_rtx (SImode);
-  operands[5] = GEN_INT (-2147483647 - 1);
+  rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
+  DONE;
 }")
 
 (define_expand "umaxsi3"
@@ -2026,104 +1947,13 @@ (define_expand "umaxsi3"
 				       (minus:SI (match_dup 4) (match_dup 3))))
    (set (match_operand:SI 0 "gpc_reg_operand" "")
 	(plus:SI (match_dup 3) (match_dup 1)))]
-  "TARGET_POWER || TARGET_ISEL"
+  "TARGET_ISEL"
   "
 {
-  if (TARGET_ISEL)
-    {
-      rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
-      DONE;
-    }
-  operands[3] = gen_reg_rtx (SImode);
-  operands[4] = gen_reg_rtx (SImode);
-  operands[5] = GEN_INT (-2147483647 - 1);
+  rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
+  DONE;
 }")
 
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
-			     (match_operand:SI 2 "reg_or_short_operand" "rI"))
-			 (const_int 0)
-			 (minus:SI (match_dup 2) (match_dup 1))))]
-  "TARGET_POWER"
-  "doz%I2 %0,%1,%2")
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			      (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
-			  (const_int 0)
-			  (minus:SI (match_dup 2) (match_dup 1)))
-	 (const_int 0)))
-   (clobber (match_scratch:SI 3 "=r,r"))]
-  "TARGET_POWER"
-  "@
-   doz%I2. %3,%1,%2
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
-			      (match_operand:SI 2 "reg_or_short_operand" ""))
-			  (const_int 0)
-			  (minus:SI (match_dup 2) (match_dup 1)))
-	 (const_int 0)))
-   (clobber (match_scratch:SI 3 ""))]
-  "TARGET_POWER && reload_completed"
-  [(set (match_dup 3)
-	(if_then_else:SI (gt (match_dup 1) (match_dup 2))
-			  (const_int 0)
-			  (minus:SI (match_dup 2) (match_dup 1))))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			      (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
-			  (const_int 0)
-			  (minus:SI (match_dup 2) (match_dup 1)))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(if_then_else:SI (gt (match_dup 1) (match_dup 2))
-			 (const_int 0)
-			 (minus:SI (match_dup 2) (match_dup 1))))]
-  "TARGET_POWER"
-  "@
-   doz%I2. %0,%1,%2
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
-			      (match_operand:SI 2 "reg_or_short_operand" ""))
-			  (const_int 0)
-			  (minus:SI (match_dup 2) (match_dup 1)))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(if_then_else:SI (gt (match_dup 1) (match_dup 2))
-			 (const_int 0)
-			 (minus:SI (match_dup 2) (match_dup 1))))]
-  "TARGET_POWER && reload_completed"
-  [(set (match_dup 0)
-	(if_then_else:SI (gt (match_dup 1) (match_dup 2))
-			 (const_int 0)
-			 (minus:SI (match_dup 2) (match_dup 1))))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
 ;; We don't need abs with condition code because such comparisons should
 ;; never be done.
 (define_expand "abssi2"
@@ -2137,19 +1967,13 @@ (define_expand "abssi2"
       emit_insn (gen_abssi2_isel (operands[0], operands[1]));
       DONE;
     }
-  else if (! TARGET_POWER)
+  else
     {
       emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
       DONE;
     }
 }")
 
-(define_insn "*abssi2_power"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
-  "TARGET_POWER"
-  "abs %0,%1")
-
 (define_insn_and_split "abs<mode>2_isel"
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
         (abs:GPR (match_operand:GPR 1 "gpc_reg_operand" "b")))
@@ -2192,7 +2016,7 @@ (define_insn_and_split "abssi2_nopower"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
         (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
    (clobber (match_scratch:SI 2 "=&r,&r"))]
-  "! TARGET_POWER && ! TARGET_ISEL"
+  "! TARGET_ISEL"
   "#"
   "&& reload_completed"
   [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
@@ -2200,17 +2024,11 @@ (define_insn_and_split "abssi2_nopower"
    (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
   "")
 
-(define_insn "*nabs_power"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
-  "TARGET_POWER"
-  "nabs %0,%1")
-
 (define_insn_and_split "*nabs_nopower"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
         (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
    (clobber (match_scratch:SI 2 "=&r,&r"))]
-  "! TARGET_POWER"
+  ""
   "#"
   "&& reload_completed"
   [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
@@ -2816,41 +2634,11 @@ (define_split
   emit_insn (gen_bswapsi2 (dest_low, src_high));
 }")
 
-(define_expand "mulsi3"
-  [(use (match_operand:SI 0 "gpc_reg_operand" ""))
-   (use (match_operand:SI 1 "gpc_reg_operand" ""))
-   (use (match_operand:SI 2 "reg_or_short_operand" ""))]
-  ""
-  "
-{
-  if (TARGET_POWER)
-    emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
-  else
-    emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
-  DONE;
-}")
-
-(define_insn "mulsi3_mq"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
-		 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
-   (clobber (match_scratch:SI 3 "=q,q"))]
-  "TARGET_POWER"
-  "@
-   {muls|mullw} %0,%1,%2
-   {muli|mulli} %0,%1,%2"
-   [(set (attr "type")
-      (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
-		(const_string "imul3")
-             (match_operand:SI 2 "short_cint_operand" "")
-		(const_string "imul2")]
-	(const_string "imul")))])
-
-(define_insn "mulsi3_no_mq"
+(define_insn "mulsi3"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
 	(mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
 		 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
-  "! TARGET_POWER"
+  ""
   "@
    {muls|mullw} %0,%1,%2
    {muli|mulli} %0,%1,%2"
@@ -2861,43 +2649,13 @@ (define_insn "mulsi3_no_mq"
 		(const_string "imul2")]
 	(const_string "imul")))])
 
-(define_insn "*mulsi3_mq_internal1"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
-			     (match_operand:SI 2 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 "=r,r"))
-   (clobber (match_scratch:SI 4 "=q,q"))]
-  "TARGET_POWER"
-  "@
-   {muls.|mullw.} %3,%1,%2
-   #"
-  [(set_attr "type" "imul_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			     (match_operand:SI 2 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 ""))
-   (clobber (match_scratch:SI 4 ""))]
-  "TARGET_POWER && reload_completed"
-  [(parallel [(set (match_dup 3)
-	(mult:SI (match_dup 1) (match_dup 2)))
-   (clobber (match_dup 4))])
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*mulsi3_no_mq_internal1"
+(define_insn "*mulsi3_internal1"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
 	(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
 			     (match_operand:SI 2 "gpc_reg_operand" "r,r"))
 		    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r,r"))]
-  "! TARGET_POWER"
+  ""
   "@
    {muls.|mullw.} %3,%1,%2
    #"
@@ -2910,7 +2668,7 @@ (define_split
 			     (match_operand:SI 2 "gpc_reg_operand" ""))
 		    (const_int 0)))
    (clobber (match_scratch:SI 3 ""))]
-  "! TARGET_POWER && reload_completed"
+  "reload_completed"
   [(set (match_dup 3)
 	(mult:SI (match_dup 1) (match_dup 2)))
    (set (match_dup 0)
@@ -2918,46 +2676,14 @@ (define_split
 		    (const_int 0)))]
   "")
 
-(define_insn "*mulsi3_mq_internal2"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
-			     (match_operand:SI 2 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(mult:SI (match_dup 1) (match_dup 2)))
-   (clobber (match_scratch:SI 4 "=q,q"))]
-  "TARGET_POWER"
-  "@
-   {muls.|mullw.} %0,%1,%2
-   #"
-  [(set_attr "type" "imul_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			     (match_operand:SI 2 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(mult:SI (match_dup 1) (match_dup 2)))
-   (clobber (match_scratch:SI 4 ""))]
-  "TARGET_POWER && reload_completed"
-  [(parallel [(set (match_dup 0)
-	(mult:SI (match_dup 1) (match_dup 2)))
-   (clobber (match_dup 4))])
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*mulsi3_no_mq_internal2"
+(define_insn "*mulsi3_internal2"
   [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
 	(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
 			     (match_operand:SI 2 "gpc_reg_operand" "r,r"))
 		    (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
 	(mult:SI (match_dup 1) (match_dup 2)))]
-  "! TARGET_POWER"
+  ""
   "@
    {muls.|mullw.} %0,%1,%2
    #"
@@ -2971,7 +2697,7 @@ (define_split
 		    (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "")
 	(mult:SI (match_dup 1) (match_dup 2)))]
-  "! TARGET_POWER && reload_completed"
+  "reload_completed"
   [(set (match_dup 0)
 	(mult:SI (match_dup 1) (match_dup 2)))
    (set (match_dup 3)
@@ -2989,38 +2715,25 @@ (define_expand "divmodsi4"
 			   (match_operand:SI 2 "gpc_reg_operand" "")))
 	      (set (match_operand:SI 3 "register_operand" "")
 		   (mod:SI (match_dup 1) (match_dup 2)))])]
-  "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
+  "! TARGET_POWERPC"
   "
 {
-  if (! TARGET_POWER && ! TARGET_POWERPC)
-    {
-      emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
-      emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
-      emit_insn (gen_divss_call ());
-      emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
-      emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
-      DONE;
-    }
+  emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
+  emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
+  emit_insn (gen_divss_call ());
+  emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
+  emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
+  DONE;
 }")
 
-(define_insn "*divmodsi4_internal"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-		(match_operand:SI 2 "gpc_reg_operand" "r")))
-   (set (match_operand:SI 3 "register_operand" "=q")
-	(mod:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_POWER"
-  "divs %0,%1,%2"
-  [(set_attr "type" "idiv")])
-
 (define_expand "udiv<mode>3"
   [(set (match_operand:GPR 0 "gpc_reg_operand" "")
         (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
 		  (match_operand:GPR 2 "gpc_reg_operand" "")))]
-  "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
+  ""
   "
 {
-  if (! TARGET_POWER && ! TARGET_POWERPC)
+  if (! TARGET_POWERPC)
     {
       emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
       emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
@@ -3028,27 +2741,13 @@ (define_expand "udiv<mode>3"
       emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
       DONE;
     }
-  else if (TARGET_POWER)
-    {
-      emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
-      DONE;
-    }
 }")
 
-(define_insn "udivsi3_mq"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-        (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-                 (match_operand:SI 2 "gpc_reg_operand" "r")))
-   (clobber (match_scratch:SI 3 "=q"))]
-  "TARGET_POWERPC && TARGET_POWER"
-  "divwu %0,%1,%2"
-  [(set_attr "type" "idiv")])
-
-(define_insn "*udivsi3_no_mq"
+(define_insn "*udivsi3"
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
         (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
 		  (match_operand:GPR 2 "gpc_reg_operand" "r")))]
-  "TARGET_POWERPC && ! TARGET_POWER"
+  "TARGET_POWERPC"
   "div<wd>u %0,%1,%2"
    [(set (attr "type")
       (cond [(match_operand:SI 0 "" "")
@@ -3057,9 +2756,8 @@ (define_insn "*udivsi3_no_mq"
 
 
 ;; For powers of two we can do srai/aze for divide and then adjust for
-;; modulus.  If it isn't a power of two, FAIL on POWER so divmodsi4 will be
-;; used; for PowerPC, force operands into register and do a normal divide;
-;; for AIX common-mode, use quoss call on register operands.
+;; modulus.  If it isn't a power of two, force operands into register and do
+;; a normal divide; for AIX common-mode, use quoss call on register operands.
 (define_expand "div<mode>3"
   [(set (match_operand:GPR 0 "gpc_reg_operand" "")
 	(div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
@@ -3074,14 +2772,7 @@ (define_expand "div<mode>3"
   else if (TARGET_POWERPC)
     {
       operands[2] = force_reg (<MODE>mode, operands[2]);
-      if (TARGET_POWER)
-	{
-	  emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
-	  DONE;
-	}
     }
-  else if (TARGET_POWER)
-    FAIL;
   else
     {
       emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
@@ -3092,20 +2783,11 @@ (define_expand "div<mode>3"
     }
 }")
 
-(define_insn "divsi3_mq"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-        (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-                (match_operand:SI 2 "gpc_reg_operand" "r")))
-   (clobber (match_scratch:SI 3 "=q"))]
-  "TARGET_POWERPC && TARGET_POWER"
-  "divw %0,%1,%2"
-  [(set_attr "type" "idiv")])
-
 (define_insn "*div<mode>3_no_mq"
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
         (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
 		 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
-  "TARGET_POWERPC && ! TARGET_POWER"
+  "TARGET_POWERPC"
   "div<wd> %0,%1,%2"
   [(set (attr "type")
      (cond [(match_operand:SI 0 "" "")
@@ -3206,63 +2888,6 @@ (define_split
 		    (const_int 0)))]
   "")
 
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(udiv:SI
-	 (plus:DI (ashift:DI
-		   (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
-		   (const_int 32))
-		  (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
-	 (match_operand:SI 3 "gpc_reg_operand" "r")))
-   (set (match_operand:SI 2 "register_operand" "=*q")
-	(umod:SI
-	 (plus:DI (ashift:DI
-		   (zero_extend:DI (match_dup 1)) (const_int 32))
-		  (zero_extend:DI (match_dup 4)))
-	 (match_dup 3)))]
-  "TARGET_POWER"
-  "div %0,%1,%3"
-  [(set_attr "type" "idiv")])
-
-;; To do unsigned divide we handle the cases of the divisor looking like a
-;; negative number.  If it is a constant that is less than 2**31, we don't
-;; have to worry about the branches.  So make a few subroutines here.
-;;
-;; First comes the normal case.
-(define_expand "udivmodsi4_normal"
-  [(set (match_dup 4) (const_int 0))
-   (parallel [(set (match_operand:SI 0 "" "")
-		   (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
-						(const_int 32))
-				     (zero_extend:DI (match_operand:SI 1 "" "")))
-			    (match_operand:SI 2 "" "")))
-	      (set (match_operand:SI 3 "" "")
-		   (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
-						(const_int 32))
-				     (zero_extend:DI (match_dup 1)))
-			    (match_dup 2)))])]
-  "TARGET_POWER"
-  "
-{ operands[4] = gen_reg_rtx (SImode); }")
-
-;; This handles the branches.
-(define_expand "udivmodsi4_tests"
-  [(set (match_operand:SI 0 "" "") (const_int 0))
-   (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
-   (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
-   (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
-			   (label_ref (match_operand:SI 4 "" "")) (pc)))
-   (set (match_dup 0) (const_int 1))
-   (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
-   (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
-   (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
-			   (label_ref (match_dup 4)) (pc)))]
-  "TARGET_POWER"
-  "
-{ operands[5] = gen_reg_rtx (CCUNSmode);
-  operands[6] = gen_reg_rtx (CCmode);
-}")
-
 (define_expand "udivmodsi4"
   [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
 		   (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
@@ -3272,39 +2897,17 @@ (define_expand "udivmodsi4"
   ""
   "
 {
-  rtx label = 0;
-
-  if (! TARGET_POWER)
-    {
-      if (! TARGET_POWERPC)
-        {
-	  emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
-	  emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
-	  emit_insn (gen_divus_call ());
-	  emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
-	  emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
-	  DONE;
-        }
-      else
-        FAIL;
-    }
-
-  if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
+  if (! TARGET_POWERPC)
     {
-      operands[2] = force_reg (SImode, operands[2]);
-      label = gen_label_rtx ();
-      emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
-				  operands[3], label));
+      emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
+      emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
+      emit_insn (gen_divus_call ());
+      emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
+      emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
+      DONE;
     }
   else
-    operands[2] = force_reg (SImode, operands[2]);
-
-  emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
-			       operands[3]));
-  if (label)
-    emit_label (label);
-
-  DONE;
+    FAIL;
 }")
 
 ;; AIX architecture-independent common-mode multiply (DImode),
@@ -3319,7 +2922,7 @@ (define_insn "mulh_call"
 			       (sign_extend:DI (reg:SI 4)))
 		      (const_int 32))))
    (clobber (reg:SI LR_REGNO))]
-  "! TARGET_POWER && ! TARGET_POWERPC"
+  "! TARGET_POWERPC"
   "bla __mulh"
   [(set_attr "type" "imul")])
 
@@ -3329,7 +2932,7 @@ (define_insn "mull_call"
 		 (sign_extend:DI (reg:SI 4))))
    (clobber (reg:SI LR_REGNO))
    (clobber (reg:SI 0))]
-  "! TARGET_POWER && ! TARGET_POWERPC"
+  "! TARGET_POWERPC"
   "bla __mull"
   [(set_attr "type" "imul")])
 
@@ -3340,7 +2943,7 @@ (define_insn "divss_call"
 	(mod:SI (reg:SI 3) (reg:SI 4)))
    (clobber (reg:SI LR_REGNO))
    (clobber (reg:SI 0))]
-  "! TARGET_POWER && ! TARGET_POWERPC"
+  "! TARGET_POWERPC"
   "bla __divss"
   [(set_attr "type" "idiv")])
 
@@ -3353,7 +2956,7 @@ (define_insn "divus_call"
    (clobber (reg:SI 0))
    (clobber (match_scratch:CC 0 "=x"))
    (clobber (reg:CC CR1_REGNO))]
-  "! TARGET_POWER && ! TARGET_POWERPC"
+  "! TARGET_POWERPC"
   "bla __divus"
   [(set_attr "type" "idiv")])
 
@@ -3361,7 +2964,7 @@ (define_insn "quoss_call"
   [(set (reg:SI 3)
 	(div:SI (reg:SI 3) (reg:SI 4)))
    (clobber (reg:SI LR_REGNO))]
-  "! TARGET_POWER && ! TARGET_POWERPC"
+  "! TARGET_POWERPC"
   "bla __quoss"
   [(set_attr "type" "idiv")])
 
@@ -3372,7 +2975,7 @@ (define_insn "quous_call"
    (clobber (reg:SI 0))
    (clobber (match_scratch:CC 0 "=x"))
    (clobber (reg:CC CR1_REGNO))]
-  "! TARGET_POWER && ! TARGET_POWERPC"
+  "! TARGET_POWERPC"
   "bla __quous"
   [(set_attr "type" "idiv")])
 
@@ -3881,198 +3484,6 @@ (define_split
 	(compare:CC (match_dup 0)
 		    (const_int 0)))]
   "")
-
-;; maskir insn.  We need four forms because things might be in arbitrary
-;; orders.  Don't define forms that only set CR fields because these
-;; would modify an input register.
-
-(define_insn "*maskir_internal1"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
-			(match_operand:SI 1 "gpc_reg_operand" "0"))
-		(and:SI (match_dup 2)
-			(match_operand:SI 3 "gpc_reg_operand" "r"))))]
-  "TARGET_POWER"
-  "maskir %0,%3,%2")
-
-(define_insn "*maskir_internal2"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
-			(match_operand:SI 1 "gpc_reg_operand" "0"))
-		(and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
-			(match_dup 2))))]
-  "TARGET_POWER"
-  "maskir %0,%3,%2")
-
-(define_insn "*maskir_internal3"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
-			(match_operand:SI 3 "gpc_reg_operand" "r"))
-		(and:SI (not:SI (match_dup 2))
-			(match_operand:SI 1 "gpc_reg_operand" "0"))))]
-  "TARGET_POWER"
-  "maskir %0,%3,%2")
-
-(define_insn "*maskir_internal4"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
-			(match_operand:SI 2 "gpc_reg_operand" "r"))
-		(and:SI (not:SI (match_dup 2))
-			(match_operand:SI 1 "gpc_reg_operand" "0"))))]
-  "TARGET_POWER"
-  "maskir %0,%3,%2")
-
-(define_insn "*maskir_internal5"
-  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
-			 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
-		 (and:SI (match_dup 2)
-			 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
-		(and:SI (match_dup 2) (match_dup 3))))]
-  "TARGET_POWER"
-  "@
-   maskir. %0,%3,%2
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
-			 (match_operand:SI 1 "gpc_reg_operand" ""))
-		 (and:SI (match_dup 2)
-			 (match_operand:SI 3 "gpc_reg_operand" "")))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
-		(and:SI (match_dup 2) (match_dup 3))))]
-  "TARGET_POWER && reload_completed"
-  [(set (match_dup 0)
-	(ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
-		(and:SI (match_dup 2) (match_dup 3))))
-   (set (match_dup 4)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*maskir_internal6"
-  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
-			 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
-		 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
-			 (match_dup 2)))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
-		(and:SI (match_dup 3) (match_dup 2))))]
-  "TARGET_POWER"
-  "@
-   maskir. %0,%3,%2
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
-			 (match_operand:SI 1 "gpc_reg_operand" ""))
-		 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
-			 (match_dup 2)))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
-		(and:SI (match_dup 3) (match_dup 2))))]
-  "TARGET_POWER && reload_completed"
-  [(set (match_dup 0)
-	(ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
-		(and:SI (match_dup 3) (match_dup 2))))
-   (set (match_dup 4)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*maskir_internal7"
-  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
-			 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
-		 (and:SI (not:SI (match_dup 2))
-			 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(ior:SI (and:SI (match_dup 2) (match_dup 3))
-		(and:SI (not:SI (match_dup 2)) (match_dup 1))))]
-  "TARGET_POWER"
-  "@
-   maskir. %0,%3,%2
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
-			 (match_operand:SI 3 "gpc_reg_operand" ""))
-		 (and:SI (not:SI (match_dup 2))
-			 (match_operand:SI 1 "gpc_reg_operand" "")))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(ior:SI (and:SI (match_dup 2) (match_dup 3))
-		(and:SI (not:SI (match_dup 2)) (match_dup 1))))]
-  "TARGET_POWER && reload_completed"
-  [(set (match_dup 0)
-	(ior:SI (and:SI (match_dup 2) (match_dup 3))
-		(and:SI (not:SI (match_dup 2)) (match_dup 1))))
-   (set (match_dup 4)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*maskir_internal8"
-  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
-			 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
-		 (and:SI (not:SI (match_dup 2))
-			 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(ior:SI (and:SI (match_dup 3) (match_dup 2))
-		(and:SI (not:SI (match_dup 2)) (match_dup 1))))]
-  "TARGET_POWER"
-  "@
-   maskir. %0,%3,%2
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
-			 (match_operand:SI 2 "gpc_reg_operand" ""))
-		 (and:SI (not:SI (match_dup 2))
-			 (match_operand:SI 1 "gpc_reg_operand" "")))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(ior:SI (and:SI (match_dup 3) (match_dup 2))
-		(and:SI (not:SI (match_dup 2)) (match_dup 1))))]
-  "TARGET_POWER && reload_completed"
-  [(set (match_dup 0)
-	(ior:SI (and:SI (match_dup 3) (match_dup 2))
-		(and:SI (not:SI (match_dup 2)) (match_dup 1))))
-   (set (match_dup 4)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
 
 ;; Rotate and shift insns, in all their variants.  These support shifts,
 ;; field inserts and extracts, and various combinations thereof.
@@ -4833,38 +4244,11 @@ (define_split
 		    (const_int 0)))]
   "")
 
-;; Note that we use "sle." instead of "sl." so that we can set
-;; SHIFT_COUNT_TRUNCATED.
-
-(define_expand "ashlsi3"
-  [(use (match_operand:SI 0 "gpc_reg_operand" ""))
-   (use (match_operand:SI 1 "gpc_reg_operand" ""))
-   (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
-  ""
-  "
-{
-  if (TARGET_POWER)
-    emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
-  else
-    emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
-  DONE;
-}")
-
-(define_insn "ashlsi3_power"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-		   (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
-   (clobber (match_scratch:SI 3 "=q,X"))]
-  "TARGET_POWER"
-  "@
-   sle %0,%1,%2
-   {sli|slwi} %0,%1,%h2")
-
-(define_insn "ashlsi3_no_power"
+(define_insn "ashlsi3"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
 	(ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 		   (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
-  "! TARGET_POWER"
+  ""
   "@
    {sl|slw} %0,%1,%2
    {sli|slwi} %0,%1,%h2"
@@ -4886,40 +4270,8 @@ (define_insn ""
 	(compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
 			       (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
 		    (const_int 0)))
-   (clobber (match_scratch:SI 3 "=r,r,r,r"))
-   (clobber (match_scratch:SI 4 "=q,X,q,X"))]
-  "TARGET_POWER"
-  "@
-   sle. %3,%1,%2
-   {sli.|slwi.} %3,%1,%h2
-   #
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,4,8,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			       (match_operand:SI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 ""))
-   (clobber (match_scratch:SI 4 ""))]
-  "TARGET_POWER && reload_completed"
-  [(parallel [(set (match_dup 3)
-	(ashift:SI (match_dup 1) (match_dup 2)))
-   (clobber (match_dup 4))])
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-			       (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
-		    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r,r,r,r"))]
-  "! TARGET_POWER && TARGET_32BIT"
+  "TARGET_32BIT"
   "@
    {sl.|slw.} %3,%1,%2
    {sli.|slwi.} %3,%1,%h2
@@ -4934,7 +4286,7 @@ (define_split
 			       (match_operand:SI 2 "reg_or_cint_operand" ""))
 		    (const_int 0)))
    (clobber (match_scratch:SI 3 ""))]
-  "! TARGET_POWER && TARGET_32BIT && reload_completed"
+  "TARGET_32BIT && reload_completed"
   [(set (match_dup 3)
 	(ashift:SI (match_dup 1) (match_dup 2)))
    (set (match_dup 0)
@@ -4948,42 +4300,8 @@ (define_insn ""
 			       (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
 		    (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
-	(ashift:SI (match_dup 1) (match_dup 2)))
-   (clobber (match_scratch:SI 4 "=q,X,q,X"))]
-  "TARGET_POWER"
-  "@
-   sle. %0,%1,%2
-   {sli.|slwi.} %0,%1,%h2
-   #
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,4,8,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			       (match_operand:SI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(ashift:SI (match_dup 1) (match_dup 2)))
-   (clobber (match_scratch:SI 4 ""))]
-  "TARGET_POWER && reload_completed"
-  [(parallel [(set (match_dup 0)
-	(ashift:SI (match_dup 1) (match_dup 2)))
-   (clobber (match_dup 4))])
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-			       (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
 	(ashift:SI (match_dup 1) (match_dup 2)))]
-  "! TARGET_POWER && TARGET_32BIT"
+  "TARGET_32BIT"
   "@
    {sl.|slw.} %0,%1,%2
    {sli.|slwi.} %0,%1,%h2
@@ -4999,7 +4317,7 @@ (define_split
 		    (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "")
 	(ashift:SI (match_dup 1) (match_dup 2)))]
-  "! TARGET_POWER && TARGET_32BIT && reload_completed"
+  "TARGET_32BIT && reload_completed"
   [(set (match_dup 0)
 	(ashift:SI (match_dup 1) (match_dup 2)))
    (set (match_dup 3)
@@ -5080,38 +4398,11 @@ (define_split
 		    (const_int 0)))]
   "")
 
-;; The AIX assembler mis-handles "sri x,x,0", so write that case as
-;; "sli x,x,0".
-(define_expand "lshrsi3"
-  [(use (match_operand:SI 0 "gpc_reg_operand" ""))
-   (use (match_operand:SI 1 "gpc_reg_operand" ""))
-   (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
-  ""
-  "
-{
-  if (TARGET_POWER)
-    emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
-  else
-    emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
-  DONE;
-}")
-
-(define_insn "lshrsi3_power"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
-	(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
-		     (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
-   (clobber (match_scratch:SI 3 "=q,X,X"))]
-  "TARGET_POWER"
-  "@
-  sre %0,%1,%2
-  mr %0,%1
-  {s%A2i|s%A2wi} %0,%1,%h2")
-
-(define_insn "lshrsi3_no_power"
+(define_insn "lshrsi3"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
 	(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
 		     (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
-  "! TARGET_POWER"
+  ""
   "@
   mr %0,%1
   {sr|srw} %0,%1,%2
@@ -5132,44 +4423,10 @@ (define_insn "*lshrsi3_64"
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
 	(compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
-				 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
-   (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
-  "TARGET_POWER"
-  "@
-  sre. %3,%1,%2
-  mr. %1,%1
-  {s%A2i.|s%A2wi.} %3,%1,%h2
-  #
-  #
-  #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,4,4,8,8,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
-				 (match_operand:SI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 ""))
-   (clobber (match_scratch:SI 4 ""))]
-  "TARGET_POWER && reload_completed"
-  [(parallel [(set (match_dup 3)
-	(lshiftrt:SI (match_dup 1) (match_dup 2)))
-   (clobber (match_dup 4))])
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
-	(compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
 				 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
 		    (const_int 0)))
    (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
-  "! TARGET_POWER && TARGET_32BIT"
+  "TARGET_32BIT"
   "@
    mr. %1,%1
    {sr.|srw.} %3,%1,%2
@@ -5186,7 +4443,7 @@ (define_split
 				 (match_operand:SI 2 "reg_or_cint_operand" ""))
 		    (const_int 0)))
    (clobber (match_scratch:SI 3 ""))]
-  "! TARGET_POWER && TARGET_32BIT && reload_completed"
+  "TARGET_32BIT && reload_completed"
   [(set (match_dup 3)
 	(lshiftrt:SI (match_dup 1) (match_dup 2)))
    (set (match_dup 0)
@@ -5197,47 +4454,11 @@ (define_split
 (define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
 	(compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
-				 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
-	(lshiftrt:SI (match_dup 1) (match_dup 2)))
-   (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
-  "TARGET_POWER"
-  "@
-  sre. %0,%1,%2
-  mr. %0,%1
-  {s%A2i.|s%A2wi.} %0,%1,%h2
-  #
-  #
-  #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,4,4,8,8,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
-				 (match_operand:SI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(lshiftrt:SI (match_dup 1) (match_dup 2)))
-   (clobber (match_scratch:SI 4 ""))]
-  "TARGET_POWER && reload_completed"
-  [(parallel [(set (match_dup 0)
-	(lshiftrt:SI (match_dup 1) (match_dup 2)))
-   (clobber (match_dup 4))])
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
-	(compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
 				 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
 		    (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
 	(lshiftrt:SI (match_dup 1) (match_dup 2)))]
-  "! TARGET_POWER && TARGET_32BIT"
+  "TARGET_32BIT"
   "@
    mr. %0,%1
    {sr.|srw.} %0,%1,%2
@@ -5255,7 +4476,7 @@ (define_split
 		    (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "")
 	(lshiftrt:SI (match_dup 1) (match_dup 2)))]
-  "! TARGET_POWER && TARGET_32BIT && reload_completed"
+  "TARGET_32BIT && reload_completed"
   [(set (match_dup 0)
 	(lshiftrt:SI (match_dup 1) (match_dup 2)))
    (set (match_dup 3)
@@ -5494,64 +4715,11 @@ (define_split
 		    (const_int 0)))]
   "")
 
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
-			 (const_int 1)
-			 (match_operand:SI 1 "gpc_reg_operand" "r"))
-	(ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
-		     (const_int 31)))]
-  "TARGET_POWER"
-  "rrib %0,%1,%2")
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
-			 (const_int 1)
-			 (match_operand:SI 1 "gpc_reg_operand" "r"))
-	(lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
-		     (const_int 31)))]
-  "TARGET_POWER"
-  "rrib %0,%1,%2")
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
-			 (const_int 1)
-			 (match_operand:SI 1 "gpc_reg_operand" "r"))
-	(zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
-			 (const_int 1)
-			 (const_int 0)))]
-  "TARGET_POWER"
-  "rrib %0,%1,%2")
-
-(define_expand "ashrsi3"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
-		     (match_operand:SI 2 "reg_or_cint_operand" "")))]
-  ""
-  "
-{
-  if (TARGET_POWER)
-    emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
-  else
-    emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
-  DONE;
-}")
-
-(define_insn "ashrsi3_power"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-		     (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
-   (clobber (match_scratch:SI 3 "=q,X"))]
-  "TARGET_POWER"
-  "@
-   srea %0,%1,%2
-   {srai|srawi} %0,%1,%h2"
-  [(set_attr "type" "shift")])
-
-(define_insn "ashrsi3_no_power"
+(define_insn "ashrsi3"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
 	(ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 		     (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
-  "! TARGET_POWER"
+  ""
   "@
    {sra|sraw} %0,%1,%2
    {srai|srawi} %0,%1,%h2"
@@ -5573,104 +4741,38 @@ (define_insn ""
 	(compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
 				 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
 		    (const_int 0)))
-   (clobber (match_scratch:SI 3 "=r,r,r,r"))
-   (clobber (match_scratch:SI 4 "=q,X,q,X"))]
-  "TARGET_POWER"
+   (clobber (match_scratch:SI 3 "=r,r,r,r"))]
+  ""
   "@
-   srea. %3,%1,%2
+   {sra.|sraw.} %3,%1,%2
    {srai.|srawi.} %3,%1,%h2
    #
    #"
-  [(set_attr "type" "delayed_compare")
+  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
    (set_attr "length" "4,4,8,8")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
 	(compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
 				 (match_operand:SI 2 "reg_or_cint_operand" ""))
 		    (const_int 0)))
-   (clobber (match_scratch:SI 3 ""))
-   (clobber (match_scratch:SI 4 ""))]
-  "TARGET_POWER && reload_completed"
-  [(parallel [(set (match_dup 3)
+   (clobber (match_scratch:SI 3 ""))]
+  "reload_completed"
+  [(set (match_dup 3)
 	(ashiftrt:SI (match_dup 1) (match_dup 2)))
-   (clobber (match_dup 4))])
    (set (match_dup 0)
 	(compare:CC (match_dup 3)
 		    (const_int 0)))]
   "")
 
 (define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-				 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 "=r,r,r,r"))]
-  "! TARGET_POWER"
-  "@
-   {sra.|sraw.} %3,%1,%2
-   {srai.|srawi.} %3,%1,%h2
-   #
-   #"
-  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
-   (set_attr "length" "4,4,8,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
-	(compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
-				 (match_operand:SI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 ""))]
-  "! TARGET_POWER && reload_completed"
-  [(set (match_dup 3)
-	(ashiftrt:SI (match_dup 1) (match_dup 2)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-				 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
-	(ashiftrt:SI (match_dup 1) (match_dup 2)))
-   (clobber (match_scratch:SI 4 "=q,X,q,X"))]
-  "TARGET_POWER"
-  "@
-   srea. %0,%1,%2
-   {srai.|srawi.} %0,%1,%h2
-   #
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,4,8,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
-				 (match_operand:SI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(ashiftrt:SI (match_dup 1) (match_dup 2)))
-   (clobber (match_scratch:SI 4 ""))]
-  "TARGET_POWER && reload_completed"
-  [(parallel [(set (match_dup 0)
-	(ashiftrt:SI (match_dup 1) (match_dup 2)))
-   (clobber (match_dup 4))])
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
 	(compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
 				 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
 		    (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
 	(ashiftrt:SI (match_dup 1) (match_dup 2)))]
-  "! TARGET_POWER"
+  ""
   "@
    {sra.|sraw.} %0,%1,%2
    {srai.|srawi.} %0,%1,%h2
@@ -5725,7 +4827,7 @@ (define_split
 		    (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "")
 	(ashiftrt:SI (match_dup 1) (match_dup 2)))]
-  "! TARGET_POWER && reload_completed"
+  "reload_completed"
   [(set (match_dup 0)
 	(ashiftrt:SI (match_dup 1) (match_dup 2)))
    (set (match_dup 3)
@@ -5988,7 +5090,7 @@ (define_insn "*nfmssf4_fpr"
 (define_expand "sqrtsf2"
   [(set (match_operand:SF 0 "gpc_reg_operand" "")
 	(sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
-  "(TARGET_PPC_GPOPT || TARGET_POWER2 || TARGET_XILINX_FPU)
+  "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU)
    && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
    && !TARGET_SIMPLE_FPU"
   "")
@@ -6001,14 +5103,6 @@ (define_insn ""
   "fsqrts %0,%1"
   [(set_attr "type" "ssqrt")])
 
-(define_insn ""
-  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-	(sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
-  "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS 
-   && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
-  "fsqrt %0,%1"
-  [(set_attr "type" "dsqrt")])
-
 (define_insn "*rsqrtsf_internal1"
   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
 	(unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
@@ -6379,15 +5473,13 @@ (define_insn "*nfmsdf4_fpr"
 (define_expand "sqrtdf2"
   [(set (match_operand:DF 0 "gpc_reg_operand" "")
 	(sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
-  "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS 
-   && TARGET_DOUBLE_FLOAT"
+  "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
   "")
 
 (define_insn "*sqrtdf2_fpr"
   [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
 	(sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
-  "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS 
-   && TARGET_DOUBLE_FLOAT
+  "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
    && !VECTOR_UNIT_VSX_P (DFmode)"
   "fsqrt %0,%1"
   [(set_attr "type" "dsqrt")])
@@ -6809,7 +5901,7 @@ (define_insn_and_split "*floatunssidf2_internal"
 (define_expand "fix_trunc<mode>si2"
   [(set (match_operand:SI 0 "gpc_reg_operand" "")
 	(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
-  "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT
+  "TARGET_POWERPC && TARGET_HARD_FLOAT
    && ((TARGET_FPRS && <TARGET_FLOAT>) || <E500_CONVERT>)"
   "
 {
@@ -6880,8 +5972,7 @@ (define_insn_and_split "fix_trunc<mode>si2_internal"
 	(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>")))
    (clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d"))
    (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))]
-  "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS 
-   && TARGET_DOUBLE_FLOAT"
+  "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
   "#"
   ""
   [(pc)]
@@ -6992,8 +6083,7 @@ (define_insn "fctiwz_<mode>"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
 	(unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))]
 		   UNSPEC_FCTIWZ))]
-  "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS 
-   && TARGET_DOUBLE_FLOAT"
+  "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
   "{fcirz|fctiwz} %0,%1"
   [(set_attr "type" "fp")])
 
@@ -7460,7 +6550,7 @@ (define_expand "mulsidi3"
   "! TARGET_POWERPC64"
   "
 {
-  if (! TARGET_POWER && ! TARGET_POWERPC)
+  if (! TARGET_POWERPC)
     {
       emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
       emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
@@ -7476,28 +6566,13 @@ (define_expand "mulsidi3"
 	}
       DONE;
     }
-  else if (TARGET_POWER)
-    {
-      emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
-      DONE;
-    }
 }")
 
-(define_insn "mulsidi3_mq"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
-		 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
-   (clobber (match_scratch:SI 3 "=q"))]
-  "TARGET_POWER"
-  "mul %0,%1,%2\;mfmq %L0"
-  [(set_attr "type" "imul")
-   (set_attr "length" "8")])
-
 (define_insn "*mulsidi3_no_mq"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
 	(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
 		 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
-  "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
+  "TARGET_POWERPC && ! TARGET_POWERPC64"
   "*
 {
   return (WORDS_BIG_ENDIAN)
@@ -7527,40 +6602,11 @@ (define_split
   operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
 }")
 
-(define_expand "umulsidi3"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
-		 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
-  "TARGET_POWERPC && ! TARGET_POWERPC64"
-  "
-{
-  if (TARGET_POWER)
-    {
-      emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
-      DONE;
-    }
-}")
-
-(define_insn "umulsidi3_mq"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
-	(mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
-		 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
-   (clobber (match_scratch:SI 3 "=q"))]
-  "TARGET_POWERPC && TARGET_POWER"
-  "*
-{
-  return (WORDS_BIG_ENDIAN)
-    ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
-    : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
-}"
-  [(set_attr "type" "imul")
-   (set_attr "length" "8")])
-
-(define_insn "*umulsidi3_no_mq"
+(define_insn "umulsidi3"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
 	(mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
 		 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
-  "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
+  "TARGET_POWERPC && ! TARGET_POWERPC64"
   "*
 {
   return (WORDS_BIG_ENDIAN)
@@ -7601,7 +6647,7 @@ (define_expand "smulsi3_highpart"
   ""
   "
 {
-  if (! TARGET_POWER && ! TARGET_POWERPC)
+  if (! TARGET_POWERPC)
     {
       emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
       emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
@@ -7609,26 +6655,8 @@ (define_expand "smulsi3_highpart"
       emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
       DONE;
     }
-  else if (TARGET_POWER)
-    {
-      emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
-      DONE;
-    }
 }")
 
-(define_insn "smulsi3_highpart_mq"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(truncate:SI
-	 (lshiftrt:DI (mult:DI (sign_extend:DI
-				(match_operand:SI 1 "gpc_reg_operand" "%r"))
-			       (sign_extend:DI
-				(match_operand:SI 2 "gpc_reg_operand" "r")))
-		      (const_int 32))))
-   (clobber (match_scratch:SI 3 "=q"))]
-  "TARGET_POWER"
-  "mul %0,%1,%2"
-  [(set_attr "type" "imul")])
-
 (define_insn "*smulsi3_highpart_no_mq"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(truncate:SI
@@ -7637,7 +6665,7 @@ (define_insn "*smulsi3_highpart_no_mq"
 			       (sign_extend:DI
 				(match_operand:SI 2 "gpc_reg_operand" "r")))
 		      (const_int 32))))]
-  "TARGET_POWERPC && ! TARGET_POWER"
+  "TARGET_POWERPC"
   "mulhw %0,%1,%2"
   [(set_attr "type" "imul")])
 
@@ -7650,27 +6678,7 @@ (define_expand "umulsi3_highpart"
 				(match_operand:SI 2 "gpc_reg_operand" "")))
 		      (const_int 32))))]
   "TARGET_POWERPC"
-  "
-{
-  if (TARGET_POWER)
-    {
-      emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
-      DONE;
-    }
-}")
-
-(define_insn "umulsi3_highpart_mq"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(truncate:SI
-	 (lshiftrt:DI (mult:DI (zero_extend:DI
-				(match_operand:SI 1 "gpc_reg_operand" "%r"))
-			       (zero_extend:DI
-				(match_operand:SI 2 "gpc_reg_operand" "r")))
-		      (const_int 32))))
-   (clobber (match_scratch:SI 3 "=q"))]
-  "TARGET_POWERPC && TARGET_POWER"
-  "mulhwu %0,%1,%2"
-  [(set_attr "type" "imul")])
+  "")
 
 (define_insn "*umulsi3_highpart_no_mq"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -7680,58 +6688,17 @@ (define_insn "*umulsi3_highpart_no_mq"
 			       (zero_extend:DI
 				(match_operand:SI 2 "gpc_reg_operand" "r")))
 		      (const_int 32))))]
-  "TARGET_POWERPC && ! TARGET_POWER"
+  "TARGET_POWERPC"
   "mulhwu %0,%1,%2"
   [(set_attr "type" "imul")])
 
-;; If operands 0 and 2 are in the same register, we have a problem.  But
-;; operands 0 and 1 (the usual case) can be in the same register.  That's
-;; why we have the strange constraints below.
-(define_insn "ashldi3_power"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
-	(ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
-		   (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
-   (clobber (match_scratch:SI 3 "=X,q,q,q"))]
-  "TARGET_POWER"
-  "@
-   {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
-   sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
-   sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
-   sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
-  [(set_attr "length" "8")])
-
-(define_insn "lshrdi3_power"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
-	(lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
-		     (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
-   (clobber (match_scratch:SI 3 "=X,q,q,q"))]
-  "TARGET_POWER"
-  "@
-   {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
-   sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
-   sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
-   sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
-  [(set_attr "length" "8")])
-
 ;; Shift by a variable amount is too complex to be worth open-coding.  We
 ;; just handle shifts by constants.
-(define_insn "ashrdi3_power"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
-	(ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-		     (match_operand:SI 2 "const_int_operand" "M,i")))
-   (clobber (match_scratch:SI 3 "=X,q"))]
-  "TARGET_POWER"
-  "@
-   {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
-   sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
-  [(set_attr "type" "shift")
-   (set_attr "length" "8")])
-
 (define_insn "ashrdi3_no_power"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
 	(ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
 		     (match_operand:SI 2 "const_int_operand" "M,i")))]
-  "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
+  "TARGET_32BIT && !TARGET_POWERPC64 && WORDS_BIG_ENDIAN"
   "@
    {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
    {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
@@ -8288,19 +7255,8 @@ (define_expand "ashldi3"
   [(set (match_operand:DI 0 "gpc_reg_operand" "")
 	(ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
 		   (match_operand:SI 2 "reg_or_cint_operand" "")))]
-  "TARGET_POWERPC64 || TARGET_POWER"
-  "
-{
-  if (TARGET_POWERPC64)
-    ;
-  else if (TARGET_POWER)
-    {
-      emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
-      DONE;
-    }
-  else
-    FAIL;
-}")
+  "TARGET_POWERPC64"
+  "")
 
 (define_insn "*ashldi3_internal1"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
@@ -8528,19 +7484,8 @@ (define_expand "lshrdi3"
   [(set (match_operand:DI 0 "gpc_reg_operand" "")
 	(lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
 		     (match_operand:SI 2 "reg_or_cint_operand" "")))]
-  "TARGET_POWERPC64 || TARGET_POWER"
-  "
-{
-  if (TARGET_POWERPC64)
-    ;
-  else if (TARGET_POWER)
-    {
-      emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
-      DONE;
-    }
-  else
-    FAIL;
-}")
+  "TARGET_POWERPC64"
+  "")
 
 (define_insn "*lshrdi3_internal1"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
@@ -8621,11 +7566,6 @@ (define_expand "ashrdi3"
 {
   if (TARGET_POWERPC64)
     ;
-  else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
-    {
-      emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
-      DONE;
-    }
   else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
 	   && WORDS_BIG_ENDIAN)
     {
@@ -10011,11 +8951,8 @@ (define_insn "fix_trunc_helper"
 (define_expand "fix_trunctfsi2"
   [(set (match_operand:SI 0 "gpc_reg_operand" "")
 	(fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
-  "!TARGET_IEEEQUAD
-   && (TARGET_POWER2 || TARGET_POWERPC)
-   && TARGET_HARD_FLOAT
-   && (TARGET_FPRS || TARGET_E500_DOUBLE)
-   && TARGET_LONG_DOUBLE_128"
+  "!TARGET_IEEEQUAD && TARGET_POWERPC && TARGET_HARD_FLOAT
+   && (TARGET_FPRS || TARGET_E500_DOUBLE) && TARGET_LONG_DOUBLE_128"
 {
   if (TARGET_E500_DOUBLE)
     emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
@@ -10031,8 +8968,7 @@ (define_expand "fix_trunctfsi2_fprs"
 	      (clobber (match_dup 3))
 	      (clobber (match_dup 4))
 	      (clobber (match_dup 5))])]
-  "!TARGET_IEEEQUAD
-   && (TARGET_POWER2 || TARGET_POWERPC)
+  "!TARGET_IEEEQUAD && TARGET_POWERPC
    && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
 {
   operands[2] = gen_reg_rtx (DFmode);
@@ -10299,52 +9235,12 @@ (define_split
 }")
 
 ;; TImode is similar, except that we usually want to compute the address into
-;; a register and use lsi/stsi (the exception is during reload).  MQ is also
-;; clobbered in stsi for POWER, so we need a SCRATCH for it.
-
-;; We say that MQ is clobbered in the last alternative because the first
-;; alternative would never get used otherwise since it would need a reload
-;; while the 2nd alternative would not.  We put memory cases first so they
-;; are preferred.  Otherwise, we'd try to reload the output instead of
-;; giving the SCRATCH mq.
-
-(define_insn "*movti_power"
-  [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")
-	(match_operand:TI 1 "input_operand" "r,r,Q,Y,r,n"))
-   (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
-  "TARGET_POWER && ! TARGET_POWERPC64
-   && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
-  "*
-{
-  switch (which_alternative)
-    {
-    default:
-      gcc_unreachable ();
-
-    case 0:
-      if (TARGET_STRING)
-        return \"{stsi|stswi} %1,%P0,16\";
-    case 1:
-      return \"#\";
-    case 2:
-      /* If the address is not used in the output, we can use lsi.  Otherwise,
-	 fall through to generating four loads.  */
-      if (TARGET_STRING
-	  && ! reg_overlap_mentioned_p (operands[0], operands[1]))
-	return \"{lsi|lswi} %0,%P1,16\";
-      /* ... fall through ...  */
-    case 3:
-    case 4:
-    case 5:
-      return \"#\";
-    }
-}"
-  [(set_attr "type" "store,store,load,load,*,*")])
+;; a register and use lsi/stsi (the exception is during reload).
 
 (define_insn "*movti_string"
   [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")
 	(match_operand:TI 1 "input_operand" "r,r,Q,Y,r,n"))]
-  "! TARGET_POWER && ! TARGET_POWERPC64
+  "! TARGET_POWERPC64
    && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
   "*
 {
@@ -10631,7 +9527,7 @@ (define_insn "*stmsi8"
 	  (match_operand:SI 9 "gpc_reg_operand" "r"))
      (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
 	  (match_operand:SI 10 "gpc_reg_operand" "r"))])]
-  "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
+  "TARGET_STRING && XVECLEN (operands[0], 0) == 9"
   "{stsi|stswi} %2,%1,%O0"
   [(set_attr "type" "store_ux")
    (set_attr "cell_micro" "always")])
@@ -10653,7 +9549,7 @@ (define_insn "*stmsi7"
 	  (match_operand:SI 8 "gpc_reg_operand" "r"))
      (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
 	  (match_operand:SI 9 "gpc_reg_operand" "r"))])]
-  "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
+  "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
   "{stsi|stswi} %2,%1,%O0"
   [(set_attr "type" "store_ux")
    (set_attr "cell_micro" "always")])
@@ -10673,7 +9569,7 @@ (define_insn "*stmsi6"
 	  (match_operand:SI 7 "gpc_reg_operand" "r"))
      (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
 	  (match_operand:SI 8 "gpc_reg_operand" "r"))])]
-  "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
+  "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
   "{stsi|stswi} %2,%1,%O0"
   [(set_attr "type" "store_ux")
    (set_attr "cell_micro" "always")])
@@ -10691,7 +9587,7 @@ (define_insn "*stmsi5"
 	  (match_operand:SI 6 "gpc_reg_operand" "r"))
      (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
 	  (match_operand:SI 7 "gpc_reg_operand" "r"))])]
-  "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
+  "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
   "{stsi|stswi} %2,%1,%O0"
   [(set_attr "type" "store_ux")
    (set_attr "cell_micro" "always")])
@@ -10707,7 +9603,7 @@ (define_insn "*stmsi4"
 	  (match_operand:SI 5 "gpc_reg_operand" "r"))
      (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
 	  (match_operand:SI 6 "gpc_reg_operand" "r"))])]
-  "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
+  "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
   "{stsi|stswi} %2,%1,%O0"
   [(set_attr "type" "store_ux")
    (set_attr "cell_micro" "always")])
@@ -10721,142 +9617,28 @@ (define_insn "*stmsi3"
 	  (match_operand:SI 4 "gpc_reg_operand" "r"))
      (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
 	  (match_operand:SI 5 "gpc_reg_operand" "r"))])]
-  "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
+  "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
   "{stsi|stswi} %2,%1,%O0"
   [(set_attr "type" "store_ux")
    (set_attr "cell_micro" "always")])
+
+(define_expand "setmemsi"
+  [(parallel [(set (match_operand:BLK 0 "" "")
+		   (match_operand 2 "const_int_operand" ""))
+	      (use (match_operand:SI 1 "" ""))
+	      (use (match_operand:SI 3 "" ""))])]
+  ""
+  "
+{
+  /* If value to set is not zero, use the library routine.  */
+  if (operands[2] != const0_rtx)
+    FAIL;
 
-(define_insn "*stmsi8_power"
-  [(match_parallel 0 "store_multiple_operation"
-    [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
-	  (match_operand:SI 2 "gpc_reg_operand" "r"))
-     (clobber (match_scratch:SI 3 "=q"))
-     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
-	  (match_operand:SI 4 "gpc_reg_operand" "r"))
-     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
-	  (match_operand:SI 5 "gpc_reg_operand" "r"))
-     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
-	  (match_operand:SI 6 "gpc_reg_operand" "r"))
-     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
-	  (match_operand:SI 7 "gpc_reg_operand" "r"))
-     (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
-	  (match_operand:SI 8 "gpc_reg_operand" "r"))
-     (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
-	  (match_operand:SI 9 "gpc_reg_operand" "r"))
-     (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
-	  (match_operand:SI 10 "gpc_reg_operand" "r"))])]
-  "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
-  "{stsi|stswi} %2,%1,%O0"
-  [(set_attr "type" "store_ux")
-   (set_attr "cell_micro" "always")])
-
-(define_insn "*stmsi7_power"
-  [(match_parallel 0 "store_multiple_operation"
-    [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
-	  (match_operand:SI 2 "gpc_reg_operand" "r"))
-     (clobber (match_scratch:SI 3 "=q"))
-     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
-	  (match_operand:SI 4 "gpc_reg_operand" "r"))
-     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
-	  (match_operand:SI 5 "gpc_reg_operand" "r"))
-     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
-	  (match_operand:SI 6 "gpc_reg_operand" "r"))
-     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
-	  (match_operand:SI 7 "gpc_reg_operand" "r"))
-     (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
-	  (match_operand:SI 8 "gpc_reg_operand" "r"))
-     (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
-	  (match_operand:SI 9 "gpc_reg_operand" "r"))])]
-  "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
-  "{stsi|stswi} %2,%1,%O0"
-  [(set_attr "type" "store_ux")
-   (set_attr "cell_micro" "always")])
-
-(define_insn "*stmsi6_power"
-  [(match_parallel 0 "store_multiple_operation"
-    [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
-	  (match_operand:SI 2 "gpc_reg_operand" "r"))
-     (clobber (match_scratch:SI 3 "=q"))
-     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
-	  (match_operand:SI 4 "gpc_reg_operand" "r"))
-     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
-	  (match_operand:SI 5 "gpc_reg_operand" "r"))
-     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
-	  (match_operand:SI 6 "gpc_reg_operand" "r"))
-     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
-	  (match_operand:SI 7 "gpc_reg_operand" "r"))
-     (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
-	  (match_operand:SI 8 "gpc_reg_operand" "r"))])]
-  "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
-  "{stsi|stswi} %2,%1,%O0"
-  [(set_attr "type" "store_ux")
-   (set_attr "cell_micro" "always")])
-
-(define_insn "*stmsi5_power"
-  [(match_parallel 0 "store_multiple_operation"
-    [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
-	  (match_operand:SI 2 "gpc_reg_operand" "r"))
-     (clobber (match_scratch:SI 3 "=q"))
-     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
-	  (match_operand:SI 4 "gpc_reg_operand" "r"))
-     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
-	  (match_operand:SI 5 "gpc_reg_operand" "r"))
-     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
-	  (match_operand:SI 6 "gpc_reg_operand" "r"))
-     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
-	  (match_operand:SI 7 "gpc_reg_operand" "r"))])]
-  "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
-  "{stsi|stswi} %2,%1,%O0"
-  [(set_attr "type" "store_ux")
-   (set_attr "cell_micro" "always")])
-
-(define_insn "*stmsi4_power"
-  [(match_parallel 0 "store_multiple_operation"
-    [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
-	  (match_operand:SI 2 "gpc_reg_operand" "r"))
-     (clobber (match_scratch:SI 3 "=q"))
-     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
-	  (match_operand:SI 4 "gpc_reg_operand" "r"))
-     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
-	  (match_operand:SI 5 "gpc_reg_operand" "r"))
-     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
-	  (match_operand:SI 6 "gpc_reg_operand" "r"))])]
-  "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
-  "{stsi|stswi} %2,%1,%O0"
-  [(set_attr "type" "store_ux")
-   (set_attr "cell_micro" "always")])
-
-(define_insn "*stmsi3_power"
-  [(match_parallel 0 "store_multiple_operation"
-    [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
-	  (match_operand:SI 2 "gpc_reg_operand" "r"))
-     (clobber (match_scratch:SI 3 "=q"))
-     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
-	  (match_operand:SI 4 "gpc_reg_operand" "r"))
-     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
-	  (match_operand:SI 5 "gpc_reg_operand" "r"))])]
-  "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
-  "{stsi|stswi} %2,%1,%O0"
-  [(set_attr "type" "store_ux")
-   (set_attr "cell_micro" "always")])
-
-(define_expand "setmemsi"
-  [(parallel [(set (match_operand:BLK 0 "" "")
-		   (match_operand 2 "const_int_operand" ""))
-	      (use (match_operand:SI 1 "" ""))
-	      (use (match_operand:SI 3 "" ""))])]
-  ""
-  "
-{
-  /* If value to set is not zero, use the library routine.  */
-  if (operands[2] != const0_rtx)
-    FAIL;
-
-  if (expand_block_clear (operands))
-    DONE;
-  else
-    FAIL;
-}")
+  if (expand_block_clear (operands))
+    DONE;
+  else
+    FAIL;
+}")
 
 ;; String/block move insn.
 ;; Argument 0 is the destination
@@ -10899,31 +9681,6 @@ (define_expand "movmemsi_8reg"
   "")
 
 (define_insn ""
-  [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
-	(mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
-   (use (match_operand:SI 2 "immediate_operand" "i"))
-   (use (match_operand:SI 3 "immediate_operand" "i"))
-   (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
-   (clobber (reg:SI  6))
-   (clobber (reg:SI  7))
-   (clobber (reg:SI  8))
-   (clobber (reg:SI  9))
-   (clobber (reg:SI 10))
-   (clobber (reg:SI 11))
-   (clobber (reg:SI 12))
-   (clobber (match_scratch:SI 5 "=q"))]
-  "TARGET_STRING && TARGET_POWER
-   && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
-       || INTVAL (operands[2]) == 0)
-   && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
-   && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
-   && REGNO (operands[4]) == 5"
-  "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
-  [(set_attr "type" "store_ux")
-   (set_attr "cell_micro" "always")
-   (set_attr "length" "8")])
-
-(define_insn ""
   [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
 	(mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
    (use (match_operand:SI 2 "immediate_operand" "i"))
@@ -10937,7 +9694,7 @@ (define_insn ""
    (clobber (reg:SI 11))
    (clobber (reg:SI 12))
    (clobber (match_scratch:SI 5 "=X"))]
-  "TARGET_STRING && ! TARGET_POWER
+  "TARGET_STRING
    && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
        || INTVAL (operands[2]) == 0)
    && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
@@ -10967,28 +9724,6 @@ (define_expand "movmemsi_6reg"
   "")
 
 (define_insn ""
-  [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
-	(mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
-   (use (match_operand:SI 2 "immediate_operand" "i"))
-   (use (match_operand:SI 3 "immediate_operand" "i"))
-   (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
-   (clobber (reg:SI  6))
-   (clobber (reg:SI  7))
-   (clobber (reg:SI  8))
-   (clobber (reg:SI  9))
-   (clobber (reg:SI 10))
-   (clobber (match_scratch:SI 5 "=q"))]
-  "TARGET_STRING && TARGET_POWER
-   && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
-   && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
-   && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
-   && REGNO (operands[4]) == 5"
-  "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
-  [(set_attr "type" "store_ux")
-   (set_attr "cell_micro" "always")
-   (set_attr "length" "8")])
-
-(define_insn ""
   [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
 	(mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
    (use (match_operand:SI 2 "immediate_operand" "i"))
@@ -11000,7 +9735,7 @@ (define_insn ""
    (clobber (reg:SI  9))
    (clobber (reg:SI 10))
    (clobber (match_scratch:SI 5 "=X"))]
-  "TARGET_STRING && ! TARGET_POWER
+  "TARGET_STRING
    && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
    && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
    && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
@@ -11027,26 +9762,6 @@ (define_expand "movmemsi_4reg"
   "")
 
 (define_insn ""
-  [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
-	(mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
-   (use (match_operand:SI 2 "immediate_operand" "i"))
-   (use (match_operand:SI 3 "immediate_operand" "i"))
-   (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
-   (clobber (reg:SI 6))
-   (clobber (reg:SI 7))
-   (clobber (reg:SI 8))
-   (clobber (match_scratch:SI 5 "=q"))]
-  "TARGET_STRING && TARGET_POWER
-   && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
-   && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
-   && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
-   && REGNO (operands[4]) == 5"
-  "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
-  [(set_attr "type" "store_ux")
-   (set_attr "cell_micro" "always")
-   (set_attr "length" "8")])
-
-(define_insn ""
   [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
 	(mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
    (use (match_operand:SI 2 "immediate_operand" "i"))
@@ -11056,7 +9771,7 @@ (define_insn ""
    (clobber (reg:SI 7))
    (clobber (reg:SI 8))
    (clobber (match_scratch:SI 5 "=X"))]
-  "TARGET_STRING && ! TARGET_POWER
+  "TARGET_STRING
    && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
    && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
    && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
@@ -11083,22 +9798,8 @@ (define_insn ""
    (use (match_operand:SI 2 "immediate_operand" "i"))
    (use (match_operand:SI 3 "immediate_operand" "i"))
    (clobber (match_scratch:DI 4 "=&r"))
-   (clobber (match_scratch:SI 5 "=q"))]
-  "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
-   && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
-  "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
-  [(set_attr "type" "store_ux")
-   (set_attr "cell_micro" "always")
-   (set_attr "length" "8")])
-
-(define_insn ""
-  [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
-	(mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
-   (use (match_operand:SI 2 "immediate_operand" "i"))
-   (use (match_operand:SI 3 "immediate_operand" "i"))
-   (clobber (match_scratch:DI 4 "=&r"))
    (clobber (match_scratch:SI 5 "=X"))]
-  "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
+  "TARGET_STRING && ! TARGET_POWERPC64
    && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
   "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
   [(set_attr "type" "store_ux")
@@ -11117,28 +9818,13 @@ (define_expand "movmemsi_1reg"
   "")
 
 (define_insn ""
-  [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
-	(mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
-   (use (match_operand:SI 2 "immediate_operand" "i"))
-   (use (match_operand:SI 3 "immediate_operand" "i"))
-   (clobber (match_scratch:SI 4 "=&r"))
-   (clobber (match_scratch:SI 5 "=q"))]
-  "TARGET_STRING && TARGET_POWER
-   && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
-  "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
-  [(set_attr "type" "store_ux")
-   (set_attr "cell_micro" "always")
-   (set_attr "length" "8")])
-
-(define_insn ""
   [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
 	(mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
    (use (match_operand:SI 2 "immediate_operand" "i"))
    (use (match_operand:SI 3 "immediate_operand" "i"))
    (clobber (match_scratch:SI 4 "=&r"))
    (clobber (match_scratch:SI 5 "=X"))]
-  "TARGET_STRING && ! TARGET_POWER
-   && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
+  "TARGET_STRING && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
   "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
   [(set_attr "type" "store_ux")
    (set_attr "cell_micro" "always")
@@ -11438,50 +10124,6 @@ (define_insn "*movdf_update2"
    stfdu %3,%2(%0)"
   [(set_attr "type" "fpstore_ux,fpstore_u")])
 
-;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
-
-(define_insn "*lfq_power2"
-  [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
-	(match_operand:V2DF 1 "memory_operand" ""))]
-  "TARGET_POWER2
-   && TARGET_HARD_FLOAT && TARGET_FPRS"
-  "lfq%U1%X1 %0,%1")
-
-(define_peephole2
-  [(set (match_operand:DF 0 "gpc_reg_operand" "")
-	(match_operand:DF 1 "memory_operand" ""))
-   (set (match_operand:DF 2 "gpc_reg_operand" "")
-	(match_operand:DF 3 "memory_operand" ""))]
-  "TARGET_POWER2
-   && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT 
-   && registers_ok_for_quad_peep (operands[0], operands[2])
-   && mems_ok_for_quad_peep (operands[1], operands[3])"
-  [(set (match_dup 0)
-	(match_dup 1))]
-  "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
-   operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
-
-(define_insn "*stfq_power2"
-  [(set (match_operand:V2DF 0 "memory_operand" "")
-	(match_operand:V2DF 1 "gpc_reg_operand" "f"))]
-  "TARGET_POWER2
-   && TARGET_HARD_FLOAT && TARGET_FPRS"
-  "stfq%U0%X0 %1,%0")
-
-
-(define_peephole2
-  [(set (match_operand:DF 0 "memory_operand" "")
-	(match_operand:DF 1 "gpc_reg_operand" ""))
-   (set (match_operand:DF 2 "memory_operand" "")
-	(match_operand:DF 3 "gpc_reg_operand" ""))]
-  "TARGET_POWER2
-   && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT 
-   && registers_ok_for_quad_peep (operands[1], operands[3])
-   && mems_ok_for_quad_peep (operands[0], operands[2])"
-  [(set (match_dup 0)
-	(match_dup 1))]
-  "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
-   operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
 
 ;; After inserting conditional returns we can sometimes have
 ;; unnecessary register moves.  Unfortunately we cannot have a
@@ -13688,9 +12330,9 @@ (define_insn_and_split "*eq<mode>"
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
 	(eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
 		(match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
-  "!TARGET_POWER"
+  ""
   "#"
-  "!TARGET_POWER"
+  ""
   [(set (match_dup 0)
 	(clz:GPR (match_dup 3)))
    (set (match_dup 0)
@@ -13725,9 +12367,9 @@ (define_insn_and_split "*eq<mode>_compare"
 	 (const_int 0)))
    (set (match_operand:P 0 "gpc_reg_operand" "=r")
 	(eq:P (match_dup 1) (match_dup 2)))]
-  "!TARGET_POWER && optimize_size"
+  "optimize_size"
   "#"
-  "!TARGET_POWER && optimize_size"
+  "optimize_size"
   [(set (match_dup 0)
 	(clz:P (match_dup 4)))
    (parallel [(set (match_dup 3)
@@ -13757,21 +12399,6 @@ (define_insn_and_split "*eq<mode>_compare"
     operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
   })
 
-(define_insn "*eqsi_power"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
-	(eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
-	       (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
-   (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
-  "TARGET_POWER"
-  "@
-   xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
-   {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
-   {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
-   {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
-   {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
-  [(set_attr "type" "three,two,three,three,three")
-   (set_attr "length" "12,8,12,12,12")])
-
 ;; We have insns of the form shown by the first define_insn below.  If
 ;; there is something inside the comparison operation, we must split it.
 (define_split
@@ -13932,7 +12559,7 @@ (define_insn "*ne0si"
 	(lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
 		     (const_int 31)))
    (clobber (match_scratch:SI 2 "=&r"))]
-  "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
+  "TARGET_32BIT && !TARGET_ISEL"
   "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
   [(set_attr "type" "two")
    (set_attr "length" "8")])
@@ -14127,143 +12754,6 @@ (define_split
 		    (const_int 0)))]
   "")
 
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-	       (match_operand:SI 2 "reg_or_short_operand" "r,O")))
-   (clobber (match_scratch:SI 3 "=r,X"))]
-  "TARGET_POWER"
-  "@
-   doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
-   {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
-  [(set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC
-	 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-		(match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
-	(le:SI (match_dup 1) (match_dup 2)))
-   (clobber (match_scratch:SI 3 "=r,X,r,X"))]
-  "TARGET_POWER"
-  "@
-   doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
-   {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
-   #
-   #"
-  [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
-   (set_attr "length" "12,12,16,16")])
-
-(define_split
-  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
-		(match_operand:SI 2 "reg_or_short_operand" ""))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(le:SI (match_dup 1) (match_dup 2)))
-   (clobber (match_scratch:SI 3 ""))]
-  "TARGET_POWER && reload_completed"
-  [(parallel [(set (match_dup 0)
-	(le:SI (match_dup 1) (match_dup 2)))
-   (clobber (match_dup 3))])
-   (set (match_dup 4)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
-	(plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			(match_operand:SI 2 "reg_or_short_operand" "r,O"))
-		 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
-  "TARGET_POWER"
-  "@
-   doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
-   {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
-  [(set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC
-	 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-			 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
-		  (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
-	 (const_int 0)))
-   (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
-  "TARGET_POWER"
-  "@
-   doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
-   {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
-   #
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,12,16,16")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			 (match_operand:SI 2 "reg_or_short_operand" ""))
-		  (match_operand:SI 3 "gpc_reg_operand" ""))
-	 (const_int 0)))
-   (clobber (match_scratch:SI 4 ""))]
-  "TARGET_POWER && reload_completed"
-  [(set (match_dup 4)
-	(plus:SI (le:SI (match_dup 1) (match_dup 2))
-		 (match_dup 3)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 4)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC
-	 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-			 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
-		  (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
-	(plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
-  "TARGET_POWER"
-  "@
-   doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
-   {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
-   #
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,12,16,16")])
-
-(define_split
-  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			 (match_operand:SI 2 "reg_or_short_operand" ""))
-		  (match_operand:SI 3 "gpc_reg_operand" ""))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
-  "TARGET_POWER && reload_completed"
-  [(set (match_dup 0)
-	(plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (set (match_dup 4)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-		       (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
-  "TARGET_POWER"
-  "@
-   doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
-   {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
-  [(set_attr "length" "12")])
-
 (define_insn "*leu<mode>"
   [(set (match_operand:P 0 "gpc_reg_operand" "=r")
 	(leu:P (match_operand:P 1 "gpc_reg_operand" "r")
@@ -14469,127 +12959,6 @@ (define_split
 		    (const_int 0)))]
   "")
 
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-	       (match_operand:SI 2 "reg_or_short_operand" "rI")))]
-  "TARGET_POWER"
-  "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
-   [(set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-		(match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(lt:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_POWER"
-  "@
-   doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "12,16")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
-		(match_operand:SI 2 "reg_or_short_operand" ""))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(lt:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_POWER && reload_completed"
-  [(set (match_dup 0)
-	(lt:SI (match_dup 1) (match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
-	(plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-			(match_operand:SI 2 "reg_or_short_operand" "rI"))
-		 (match_operand:SI 3 "gpc_reg_operand" "r")))]
-  "TARGET_POWER"
-  "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
-  [(set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
-		  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
-	 (const_int 0)))
-   (clobber (match_scratch:SI 4 "=&r,&r"))]
-  "TARGET_POWER"
-  "@
-   doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,16")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			 (match_operand:SI 2 "reg_or_short_operand" ""))
-		  (match_operand:SI 3 "gpc_reg_operand" ""))
-	 (const_int 0)))
-   (clobber (match_scratch:SI 4 ""))]
-  "TARGET_POWER && reload_completed"
-  [(set (match_dup 4)
-	(plus:SI (lt:SI (match_dup 1) (match_dup 2))
-		 (match_dup 3)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 4)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
-		  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
-	(plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
-  "TARGET_POWER"
-  "@
-   doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,16")])
-
-(define_split
-  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			 (match_operand:SI 2 "reg_or_short_operand" ""))
-		  (match_operand:SI 3 "gpc_reg_operand" ""))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
-  "TARGET_POWER && reload_completed"
-  [(set (match_dup 0)
-	(plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (set (match_dup 4)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-		       (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
-  "TARGET_POWER"
-  "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
-  [(set_attr "length" "12")])
-
 (define_insn_and_split "*ltu<mode>"
   [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
 	(ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
@@ -14660,131 +13029,6 @@ (define_insn "*neg_ltu<mode>"
   [(set_attr "type" "two")
    (set_attr "length" "8")])
 
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-	       (match_operand:SI 2 "reg_or_short_operand" "rI")))
-   (clobber (match_scratch:SI 3 "=r"))]
-  "TARGET_POWER"
-  "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
-   [(set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-		(match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(ge:SI (match_dup 1) (match_dup 2)))
-   (clobber (match_scratch:SI 3 "=r,r"))]
-  "TARGET_POWER"
-  "@
-   doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,16")])
-
-(define_split
-  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
-		(match_operand:SI 2 "reg_or_short_operand" ""))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(ge:SI (match_dup 1) (match_dup 2)))
-   (clobber (match_scratch:SI 3 ""))]
-  "TARGET_POWER && reload_completed"
-  [(parallel [(set (match_dup 0)
-		   (ge:SI (match_dup 1) (match_dup 2)))
-	      (clobber (match_dup 3))])
-   (set (match_dup 4)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
-	(plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-			(match_operand:SI 2 "reg_or_short_operand" "rI"))
-		 (match_operand:SI 3 "gpc_reg_operand" "r")))]
-  "TARGET_POWER"
-  "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
-  [(set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
-		  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
-	 (const_int 0)))
-   (clobber (match_scratch:SI 4 "=&r,&r"))]
-  "TARGET_POWER"
-  "@
-   doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,16")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			 (match_operand:SI 2 "reg_or_short_operand" ""))
-		  (match_operand:SI 3 "gpc_reg_operand" ""))
-	 (const_int 0)))
-   (clobber (match_scratch:SI 4 ""))]
-  "TARGET_POWER && reload_completed"
-  [(set (match_dup 4)
-	(plus:SI (ge:SI (match_dup 1) (match_dup 2))
-		 (match_dup 3)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 4)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
-		  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
-	(plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
-  "TARGET_POWER"
-  "@
-   doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,16")])
-
-(define_split
-  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			 (match_operand:SI 2 "reg_or_short_operand" ""))
-		  (match_operand:SI 3 "gpc_reg_operand" ""))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
-  "TARGET_POWER && reload_completed"
-  [(set (match_dup 0)
-	(plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (set (match_dup 4)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-		       (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
-  "TARGET_POWER"
-  "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
-  [(set_attr "length" "12")])
-
 (define_insn "*geu<mode>"
   [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
 	(geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
@@ -15007,45 +13251,6 @@ (define_split
 		    (const_int 0)))]
   "")
 
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-	       (match_operand:SI 2 "reg_or_short_operand" "r")))]
-  "TARGET_POWER"
-  "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
-  [(set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-		(match_operand:SI 2 "reg_or_short_operand" "r,r"))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(gt:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_POWER"
-  "@
-   doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "12,16")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
-		(match_operand:SI 2 "reg_or_short_operand" ""))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(gt:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_POWER && reload_completed"
-  [(set (match_dup 0)
-	(gt:SI (match_dup 1) (match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
 (define_insn "*plus_gt0<mode>"
   [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
 	(plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
@@ -15186,87 +13391,6 @@ (define_split
 		    (const_int 0)))]
   "")
 
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
-	(plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-			(match_operand:SI 2 "reg_or_short_operand" "r"))
-		 (match_operand:SI 3 "gpc_reg_operand" "r")))]
-  "TARGET_POWER"
-  "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
-  [(set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
-		  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
-	 (const_int 0)))
-   (clobber (match_scratch:SI 4 "=&r,&r"))]
-  "TARGET_POWER"
-  "@
-   doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,16")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			 (match_operand:SI 2 "reg_or_short_operand" ""))
-		  (match_operand:SI 3 "gpc_reg_operand" ""))
-	 (const_int 0)))
-   (clobber (match_scratch:SI 4 ""))]
-  "TARGET_POWER && reload_completed"
-  [(set (match_dup 4)
-	(plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 4)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
-		  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
-	(plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
-  "TARGET_POWER"
-  "@
-   doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,16")])
-
-(define_split
-  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			 (match_operand:SI 2 "reg_or_short_operand" ""))
-		  (match_operand:SI 3 "gpc_reg_operand" ""))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
-  "TARGET_POWER && reload_completed"
-  [(set (match_dup 0)
-	(plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (set (match_dup 4)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-		       (match_operand:SI 2 "reg_or_short_operand" "r"))))]
-  "TARGET_POWER"
-  "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
-  [(set_attr "length" "12")])
-
 (define_insn_and_split "*gtu<mode>"
   [(set (match_operand:P 0 "gpc_reg_operand" "=r")
 	(gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index fd3a272..5091796 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -90,18 +90,6 @@ unsigned int rs6000_debug
 TargetSave
 int rs6000_target_flags_explicit
 
-mpower
-Target Report RejectNegative Mask(POWER)
-Use POWER instruction set
-
-mno-power
-Target Report RejectNegative
-Do not use POWER instruction set
-
-mpower2
-Target Report Mask(POWER2)
-Use POWER2 instruction set
-
 mpowerpc
 Target Report RejectNegative Mask(POWERPC)
 Use PowerPC instruction set
diff --git a/gcc/config/rs6000/sysv4.h b/gcc/config/rs6000/sysv4.h
index 204f394..b9fe92b 100644
--- a/gcc/config/rs6000/sysv4.h
+++ b/gcc/config/rs6000/sysv4.h
@@ -1,7 +1,5 @@
 /* Target definitions for GNU compiler for PowerPC running System V.4
-   Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
-   2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
-   Free Software Foundation, Inc.
+   Copyright (C) 1995-2012 Free Software Foundation, Inc.
    Contributed by Cygnus Support.
 
    This file is part of GCC.
@@ -228,10 +226,6 @@ do {									\
 #undef	PROCESSOR_DEFAULT
 #define	PROCESSOR_DEFAULT PROCESSOR_PPC750
 
-/* SVR4 only defined for PowerPC, so short-circuit POWER patterns.  */
-#undef  TARGET_POWER
-#define TARGET_POWER 0
-
 #define FIXED_R2 1
 /* System V.4 uses register 13 as a pointer to the small data area,
    so it is not available to the normal user.  */
diff --git a/gcc/config/rs6000/t-aix43 b/gcc/config/rs6000/t-aix43
index c857c44..08b59b9 100644
--- a/gcc/config/rs6000/t-aix43
+++ b/gcc/config/rs6000/t-aix43
@@ -20,14 +20,12 @@
 # different processor models
 
 MULTILIB_OPTIONS	= pthread \
-			  mcpu=common/mcpu=power/mcpu=powerpc/maix64
+			  mcpu=common/mcpu=powerpc/maix64
 
 MULTILIB_DIRNAMES	= pthread \
-			  common power powerpc ppc64
+			  common powerpc ppc64
 
-MULTILIB_MATCHES	= mcpu?power=mcpu?power \
-			  mcpu?power=mcpu?power2 \
-			  mcpu?powerpc=mcpu?power3 \
+MULTILIB_MATCHES	= mcpu?powerpc=mcpu?power3 \
 			  mcpu?powerpc=mcpu?power4 \
 			  mcpu?powerpc=mcpu?powerpc \
 			  mcpu?powerpc=mcpu?rs64a \
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index cba685d..2b12ae7 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -796,7 +796,6 @@ See RS/6000 and PowerPC Options.
 @gccoptlist{-mcpu=@var{cpu-type} @gol
 -mtune=@var{cpu-type} @gol
 -mcmodel=@var{code-model} @gol
--mpower  -mno-power  -mpower2  -mno-power2 @gol
 -mpowerpc  -mpowerpc64  -mno-powerpc @gol
 -maltivec  -mno-altivec @gol
 -mpowerpc-gpopt  -mno-powerpc-gpopt @gol
@@ -16561,11 +16560,7 @@ standard hardware multiplication defined in the RL78 software manual.
 
 These @samp{-m} options are defined for the IBM RS/6000 and PowerPC:
 @table @gcctabopt
-@item -mpower
-@itemx -mno-power
-@itemx -mpower2
-@itemx -mno-power2
-@itemx -mpowerpc
+@item -mpowerpc
 @itemx -mno-powerpc
 @itemx -mpowerpc-gpopt
 @itemx -mno-powerpc-gpopt
@@ -16589,10 +16584,6 @@ These @samp{-m} options are defined for the IBM RS/6000 and PowerPC:
 @itemx -mno-mfpgpr
 @itemx -mhard-dfp
 @itemx -mno-hard-dfp
-@opindex mpower
-@opindex mno-power
-@opindex mpower2
-@opindex mno-power2
 @opindex mpowerpc
 @opindex mno-powerpc
 @opindex mpowerpc-gpopt
@@ -16633,12 +16624,6 @@ determined when configuring GCC@.  Specifying the
 options.  We recommend you use the @option{-mcpu=@var{cpu_type}} option
 rather than the options listed above.
 
-The @option{-mpower} option allows GCC to generate instructions that
-are found only in the POWER architecture and to use the MQ register.
-Specifying @option{-mpower2} implies @option{-power} and also allows GCC
-to generate instructions that are present in the POWER2 architecture but
-not the original POWER architecture.
-
 The @option{-mpowerpc} option allows GCC to generate instructions that
 are found only in the 32-bit subset of the PowerPC architecture.
 Specifying @option{-mpowerpc-gpopt} implies @option{-mpowerpc} and also allows
@@ -16677,12 +16662,9 @@ The @option{-mpowerpc64} option allows GCC to generate the additional
 and to treat GPRs as 64-bit, doubleword quantities.  GCC defaults to
 @option{-mno-powerpc64}.
 
-If you specify both @option{-mno-power} and @option{-mno-powerpc}, GCC
-uses only the instructions in the common subset of both
-architectures plus some special AIX common-mode calls, and does not use
-the MQ register.  Specifying both @option{-mpower} and @option{-mpowerpc}
-permits GCC to use any instruction from either architecture and to
-allow use of the MQ register; specify this for the Motorola MPC601.
+If you specify @option{-mno-powerpc}, GCC uses only the instructions
+in the common subset of both the POWER and PowerPC
+architectures plus some special AIX common-mode calls.
 
 @item -mnew-mnemonics
 @itemx -mold-mnemonics
@@ -16713,11 +16695,9 @@ Supported values for @var{cpu_type} are @samp{401}, @samp{403},
 @samp{860}, @samp{970}, @samp{8540}, @samp{a2}, @samp{e300c2},
 @samp{e300c3}, @samp{e500mc}, @samp{e500mc64}, @samp{e5500},
 @samp{e6500}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5},
-@samp{titan}, @samp{power}, @samp{power2}, @samp{power3},
-@samp{power4}, @samp{power5}, @samp{power5+}, @samp{power6},
-@samp{power6x}, @samp{power7}, @samp{common}, @samp{powerpc},
-@samp{powerpc64}, @samp{rios}, @samp{rios1}, @samp{rios2}, @samp{rsc},
-and @samp{rs64}.
+@samp{titan}, @samp{power3}, @samp{power4}, @samp{power5}, @samp{power5+},
+@samp{power6}, @samp{power6x}, @samp{power7}, @samp{common}, @samp{powerpc},
+@samp{powerpc64}, and @samp{rs64}.
 
 @option{-mcpu=common} selects a completely generic processor.  Code
 generated under this option runs on any POWER or PowerPC processor.
@@ -16725,9 +16705,8 @@ GCC uses only the instructions in the common subset of both
 architectures, and does not use the MQ register.  GCC assumes a generic
 processor model for scheduling purposes.
 
-@option{-mcpu=power}, @option{-mcpu=power2}, @option{-mcpu=powerpc}, and
-@option{-mcpu=powerpc64} specify generic POWER, POWER2, pure 32-bit
-PowerPC (i.e., not MPC601), and 64-bit PowerPC architecture machine
+@option{-mcpu=powerpc}, and @option{-mcpu=powerpc64} specify pure 32-bit
+PowerPC (i.e., not MPC601) and 64-bit PowerPC architecture machine
 types, with an appropriate, generic processor model assumed for
 scheduling purposes.
 
@@ -16739,7 +16718,7 @@ The @option{-mcpu} options automatically enable or disable the
 following options:
 
 @gccoptlist{-maltivec  -mfprnd  -mhard-float  -mmfcrf  -mmultiple @gol
--mnew-mnemonics  -mpopcntb -mpopcntd  -mpower  -mpower2  -mpowerpc64 @gol
+-mnew-mnemonics  -mpopcntb -mpopcntd  -mpowerpc64 @gol
 -mpowerpc-gpopt  -mpowerpc-gfxopt  -msingle-float -mdouble-float @gol
 -msimple-fpu -mstring  -mmulhw  -mdlmzb  -mmfpgpr -mvsx}
 
diff --git a/gcc/testsuite/gcc.target/powerpc/rs6000-power2-1.c b/gcc/testsuite/gcc.target/powerpc/rs6000-power2-1.c
deleted file mode 100644
index 375241e..0000000
--- a/gcc/testsuite/gcc.target/powerpc/rs6000-power2-1.c
+++ /dev/null
@@ -1,21 +0,0 @@
-/* { dg-do compile { target { ilp32 } } } */
-/* { dg-options "-O3 -mcpu=power2 -fno-schedule-insns -w -mhard-float" } */
-/* This used to ICE as the peephole was not checking to see
-   if the register is a floating point one (I think this cannot
-   happen in real life except in this example).  */
-
-register volatile double t1 __asm__("r14");
-register volatile double t2 __asm__("r15");
-register volatile double t3 __asm__("r16"), t4 __asm__("r17");
-void t(double *a, double *b)
-{
-        t1 = a[-1];
-        t2 = a[0];
-        t3 = a[1];
-        t4 = a[2];
-        b[-1] = t1;
-        b[0] = t2;
-        b[1] = t3;
-        b[2] = t4;
-}
-
diff --git a/gcc/testsuite/gcc.target/powerpc/rs6000-power2-2.c b/gcc/testsuite/gcc.target/powerpc/rs6000-power2-2.c
deleted file mode 100644
index 567ad8c..0000000
--- a/gcc/testsuite/gcc.target/powerpc/rs6000-power2-2.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/* { dg-do compile { target { powerpc_fprs && ilp32 } } } */
-/* { dg-options "-O3 -mcpu=power2 -fno-schedule-insns -w" } */
-/* { dg-final { scan-assembler-not "lfd" } } */
-/* { dg-final { scan-assembler-not "sfd" } } */
-/* { dg-final { scan-assembler "lfq" } } */
-/* { dg-final { scan-assembler "stfq" } } */
-
-register volatile double t1 __asm__("fr0");
-register volatile double t2 __asm__("fr1");
-register volatile double t3 __asm__("fr2"), t4 __asm__("fr3");
-void t(double *a, double *b)
-{
-        t1 = a[-1];
-        t2 = a[0];
-        t3 = a[1];
-        t4 = a[2];
-        b[-1] = t1;
-        b[0] = t2;
-        b[1] = t3;
-        b[2] = t4;
-}
-
