Patchwork [SH] PR 51244 - Add -mzdcbranch option

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Submitter Oleg Endo
Date July 25, 2012, 10:46 p.m.
Message ID <1343256373.2185.40.camel@yam-132-YW-E178-FTW>
Download mbox | patch
Permalink /patch/173300/
State New
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Comments

Oleg Endo - July 25, 2012, 10:46 p.m.
Hello,

This adds a new SH option -mzdcbranch / -mnozdcbranch to tell the
compiler whether zero displacement conditional branches are fast on the
target CPU.  It is enabled by default for SH4* and thus does not change
any of the established behavior.
Currently this does affect only one pattern (negsi_cond).  However, I
intent to try using it for controlling conditional execution patterns in
the future (e.g. for PR 52628).

Tested with 'make all-gcc' and 'make info dvi pdf'.

Would that be OK?

Cheers,
Oleg

ChangeLog:

	PR target/51244
	* config/sh/sh.opt (mzdcbranch): New option.
	* doc/invoke.texi: Document it.
	* config/sh/sh.md (negsi_cond): Use TARGET_ZDCBRANCH as 
	condition instead of TARGET_HARD_SH4.
	* config/sh/sh.c (sh_option_override): Set TARGET_ZDCBRANCH as 
	default for TARGET_HARD_SH4.
Kaz Kojima - July 25, 2012, 11:20 p.m.
Oleg Endo <oleg.endo@t-online.de> wrote:
> This adds a new SH option -mzdcbranch / -mnozdcbranch to tell the
> compiler whether zero displacement conditional branches are fast on the
> target CPU.  It is enabled by default for SH4* and thus does not change
> any of the established behavior.
> Currently this does affect only one pattern (negsi_cond).  However, I
> intent to try using it for controlling conditional execution patterns in
> the future (e.g. for PR 52628).
> 
> Tested with 'make all-gcc' and 'make info dvi pdf'.
> 
> Would that be OK?

OK.

Regards,
	kaz

Patch

Index: gcc/doc/invoke.texi
===================================================================
--- gcc/doc/invoke.texi	(revision 189797)
+++ gcc/doc/invoke.texi	(working copy)
@@ -889,8 +889,9 @@ 
 -mdivsi3_libfunc=@var{name} -mfixed-range=@var{register-range} @gol
 -mindexed-addressing -mgettrcost=@var{number} -mpt-fixed @gol
 -maccumulate-outgoing-args -minvalid-symbols -msoft-atomic -mhard-atomic @gol
--mbranch-cost=@var{num} -mcbranchdi -mcmpeqdi -mfused-madd -mno-fused-madd @gol
--mfsca -mno-fsca -mfsrra -mno-fsrra -mpretend-cmove -menable-tas}
+-mbranch-cost=@var{num} -mzdcbranch -mno-zdcbranch -mcbranchdi -mcmpeqdi @gol
+-mfused-madd -mno-fused-madd -mfsca -mno-fsca -mfsrra -mno-fsrra @gol
+-mpretend-cmove -menable-tas}
 
 @emph{Solaris 2 Options}
 @gccoptlist{-mimpure-text  -mno-impure-text @gol
@@ -18366,6 +18367,16 @@ 
 If not specified the value is selected depending on the processor type that
 is being compiled for.
 
+@item -mzdcbranch
+@itemx -mno-zdcbranch
+@opindex mzdcbranch
+@opindex mno-zdcbranch
+Assume (do not assume) that zero displacement conditional branch instructions
+@code{bt} and @code{bf} are fast.  If @option{-mzdcbranch} is specified, the
+compiler will try to prefer zero displacement branch code sequences.  This is
+enabled by default when generating code for SH4 and SH4A.  It can be explicitly
+disabled by specifying @option{-mno-zdcbranch}.
+
 @item -mcbranchdi
 @opindex mcbranchdi
 Enable the @code{cbranchdi4} instruction pattern.
Index: gcc/config/sh/sh.md
===================================================================
--- gcc/config/sh/sh.md	(revision 189797)
+++ gcc/config/sh/sh.md	(working copy)
@@ -4361,11 +4361,11 @@ 
 			  (match_operand:SI 3 "const_int_operand" "M,N"))
 	 (match_operand:SI 1 "arith_reg_operand" "0,0")
 	 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r,r"))))]
-  "TARGET_HARD_SH4"
+  "TARGET_SH1 && TARGET_ZDCBRANCH"
   "@
 	bt\\t0f\;neg\\t%2,%0\\n0:
 	bf\\t0f\;neg\\t%2,%0\\n0:"
-  "!TARGET_HARD_SH4"
+  "TARGET_SH1 && ! TARGET_ZDCBRANCH"
   [(const_int 0)]
 {
   rtx skip_neg_label = gen_label_rtx ();
Index: gcc/config/sh/sh.opt
===================================================================
--- gcc/config/sh/sh.opt	(revision 189797)
+++ gcc/config/sh/sh.opt	(working copy)
@@ -225,6 +225,10 @@ 
 Target RejectNegative Joined UInteger Var(sh_branch_cost) Init(-1)
 Cost to assume for a branch insn
 
+mzdcbranch
+Target Var(TARGET_ZDCBRANCH)
+Assume that zero displacement conditional branches are fast
+
 mcbranchdi
 Target Var(TARGET_CBRANCHDI4)
 Enable cbranchdi4 pattern
Index: gcc/config/sh/sh.c
===================================================================
--- gcc/config/sh/sh.c	(revision 189797)
+++ gcc/config/sh/sh.c	(working copy)
@@ -741,6 +741,10 @@ 
 	sh_branch_cost = 2;
     }
 
+  /* Set -mzdcbranch for SH4 / SH4A if not otherwise specified by the user.  */
+  if (! global_options_set.x_TARGET_ZDCBRANCH && TARGET_HARD_SH4)
+    TARGET_ZDCBRANCH = 1;
+
   for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
     if (! VALID_REGISTER_P (regno))
       sh_register_names[regno][0] = '\0';