From patchwork Tue Jul 24 16:31:26 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiang Liu X-Patchwork-Id: 172941 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 8ED3B2C0080 for ; Wed, 25 Jul 2012 02:38:18 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932083Ab2GXQfm (ORCPT ); Tue, 24 Jul 2012 12:35:42 -0400 Received: from mail-pb0-f46.google.com ([209.85.160.46]:39412 "EHLO mail-pb0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932068Ab2GXQfj (ORCPT ); Tue, 24 Jul 2012 12:35:39 -0400 Received: by mail-pb0-f46.google.com with SMTP id rp8so12916328pbb.19 for ; Tue, 24 Jul 2012 09:35:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=cWfDx1KVkXfKi78nxd8Vcy6wiBPi8jeNb5uX4dUA1tc=; b=a4Tme8LInbanE/XcJYWBxprEu2yZQrjji06zj7c94GN+/LUTws48UycNL34/NUVyhz mrIykX8SATYzwu0vZbaQEYKYFn5PQ6WalQYDNfCcmp/ZtSv11BsphMVxq0YkmenesVsE TJfzAeDy3/PE1FoBv1Wzek4YUU3oyy3B6L2vi01mqsm0LoykVIUYYq+hBXgg6dkFNWST 7xou9vH/gKdpVySUuoaoKclaihFq51x0NOjd3/IFrK0c9SeVikoXsM/PXFm0Ou3Vv+DQ opKniLryfx+b5LmXONvfJ548fZkdcUbdmlpBg9Ki2RpBe13w0rFO7OhvcdAyaq+A8bU5 dojw== Received: by 10.68.233.201 with SMTP id ty9mr45808208pbc.34.1343147739382; Tue, 24 Jul 2012 09:35:39 -0700 (PDT) Received: from localhost.localdomain ([221.221.26.244]) by mx.google.com with ESMTPS id wi6sm12457583pbc.35.2012.07.24.09.35.27 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 24 Jul 2012 09:35:34 -0700 (PDT) From: Jiang Liu To: Bjorn Helgaas , Don Dutile Cc: Jiang Liu , Yinghai Lu , Taku Izumi , "Rafael J . Wysocki" , Kenji Kaneshige , Yijing Wang , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Jiang Liu Subject: [RFC PATCH v2 14/32] PCI/tile: use PCIe capabilities access functions to simplify implementation Date: Wed, 25 Jul 2012 00:31:26 +0800 Message-Id: <1343147504-25891-15-git-send-email-jiang.liu@huawei.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1343147504-25891-1-git-send-email-jiang.liu@huawei.com> References: <1343147504-25891-1-git-send-email-jiang.liu@huawei.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Jiang Liu Use PCIe capabilities access functions to simplify PCIe tile implementation. Signed-off-by: Jiang Liu --- arch/tile/kernel/pci.c | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) diff --git a/arch/tile/kernel/pci.c b/arch/tile/kernel/pci.c index 0fdd99d..bf296cf 100644 --- a/arch/tile/kernel/pci.c +++ b/arch/tile/kernel/pci.c @@ -246,16 +246,13 @@ static void __devinit fixup_read_and_payload_sizes(void) /* Scan for the smallest maximum payload size. */ while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { - int pcie_caps_offset; u32 devcap; int max_payload; - pcie_caps_offset = pci_find_capability(dev, PCI_CAP_ID_EXP); - if (pcie_caps_offset == 0) + if (!pci_is_pcie(dev)) continue; - pci_read_config_dword(dev, pcie_caps_offset + PCI_EXP_DEVCAP, - &devcap); + pci_pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &devcap); max_payload = devcap & PCI_EXP_DEVCAP_PAYLOAD; if (max_payload < smallest_max_payload) smallest_max_payload = max_payload; @@ -264,19 +261,15 @@ static void __devinit fixup_read_and_payload_sizes(void) /* Now, set the max_payload_size for all devices to that value. */ new_values = (max_read_size << 12) | (smallest_max_payload << 5); while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { - int pcie_caps_offset; u16 devctl; - pcie_caps_offset = pci_find_capability(dev, PCI_CAP_ID_EXP); - if (pcie_caps_offset == 0) + if (!pci_is_pcie(dev)) continue; - pci_read_config_word(dev, pcie_caps_offset + PCI_EXP_DEVCTL, - &devctl); + pci_pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &devctl); devctl &= ~(PCI_EXP_DEVCTL_PAYLOAD | PCI_EXP_DEVCTL_READRQ); devctl |= new_values; - pci_write_config_word(dev, pcie_caps_offset + PCI_EXP_DEVCTL, - devctl); + pci_pcie_capability_write_word(dev, PCI_EXP_DEVCTL, devctl); } }