Intrinsics for PREFETCHW

On Tue, Jul 24, 2012 at 4:06 PM, Kirill Yukhin <kirill.yukhin@gmail.com> wrote:
>> Can you please split the patch to three independent parts, prefetchw
>> handling, rdseed and adxx. I got lost in the patch the second time.
> Sure!
>
>> I propose we start with prefetch. You are still changing prefetch
>> patterns, while it should be enough to only change prefetch expander.
> Actually, they're splitted since 3dnow has both prefetch and prefetchw
> under single CPUID bit,
> while under Intel's PRFTCH CPUID bit we have only prefetchw. So, old
> pattern "*prefetch_3dnow_<mode>"
> was set to be `prefetch` only for 3dnow, while new one is `prefetchw' only,
> working both for PRFTCH and 3DNOW bits.

Please see attached patch that does all this with minimum surgery and
also sets missing SSE prefetch for x86_32 with -mprfchw

> Changelog entry:
> 2012-07-24  Kirill Yukhin  <kirill.yukhin@intel.com>
>             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
>
>         * common/config/i386/i386-common.c (OPTION_MASK_ISA_PRFCHW_SET): New.
>         (OPTION_MASK_ISA_PRFCHW_UNSET): Likewise.
>         (ix86_handle_option): Handle mprfchw option.
>         * config.gcc (i[34567]86-*-*): Add prfchwintrin.h.
>         (x86_64-*-*): Likewise.
>         * config/i386/prfchwintrin.h: New header.
>         * config/i386/cpuid.h (bit_PRFCHW): New.
>         (bit_BMI): Formatting fix.
>         (bit_HLE): Likewise.
>         (bit_RTM): Likewise.
>         * config/i386/driver-i386.c (host_detect_local_cpu): Detect
>         PREFETCHW support.
>         * config/i386/i386-c.c: Define __PRFCHW__ if needed.
>         * config/i386/i386.c (ix86_target_string): Define
>         -mprfchw option. Formatting fixes.
>         (PTA_HLE): Formatting fix.
>         (PTA_PRFCHW): New.
>         (ix86_option_override_internal): Handle new option.
>         (ix86_valid_target_attribute_inner_p): Add OPT_mprfchw.
>         * config/i386/i386.h (TARGET_PRFCHW): New.
>         * config/i386/i386.md (prefetch): Enable for TARGET_PRFCHW.
>         (prefetchw_<mode>): New define_insn for write-prefetch.
>         (prefetch_3dnow_<mode>): Keep only read-prefetch here.
>         * config/i386/i386.opt (mprfchw): New.
>         * config/i386/mm3dnow.h: Move _m_prefetchw from here to
>         prfchwintrin.h.
>         * config/i386/x86intrin.h: Include prfchwintrin.h.
>
> testsuite/Changelog entry:
> 2012-07-24  Kirill Yukhin  <kirill.yukhin@intel.com>
>             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
>
>         * gcc.target/i386/prefetchw-1.c: New.
>         * gcc.target/i386/sse-12.c: Add -mprfchw.
>         * gcc.target/i386/sse-13.c: Ditto.
>         * gcc.target/i386/sse-14.c: Ditto.
>         * g++.dg/other/i386-2.C: Ditto.
>         * g++.dg/other/i386-3.C: Ditto.
>
> patch is bootstrapping at the moment.
>
> Any objections?

--- /dev/null
+++ b/gcc/config/i386/prfchwintrin.h

+#if !defined _X86INTRIN_H_INCLUDED && !defined _MM3DNOW_H_INCLUDED
+# error "Never use <prfchwintrin.h> directly; include <x86intrin.h>\
+or <mm3dnow.h> instead."
+#endif

No need to split the line.

Uros.
Index: i386.c
===================================================================
--- i386.c      (revision 189810)
+++ i386.c      (working copy)
@@ -3647,11 +3647,12 @@
 
   /* Turn on MMX builtins for -msse.  */
   if (TARGET_SSE)
-    {
-      ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;
-      x86_prefetch_sse = true;
-    }
+    ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;
 
+  /* Enable SSE prefetch.  */
+  if (TARGET_SSE || TARGET_PRFCHW)
+    x86_prefetch_sse = true;
+
   /* Turn on popcnt instruction for -msse4.2 or -mabm.  */
   if (TARGET_SSE4_2 || TARGET_ABM)
     ix86_isa_flags |= OPTION_MASK_ISA_POPCNT & ~ix86_isa_flags_explicit;
Index: i386.md
===================================================================
--- i386.md     (revision 189491)
+++ i386.md     (working copy)
@@ -17684,11 +17684,13 @@
   gcc_assert (GET_MODE (operands[0]) == Pmode
              || GET_MODE (operands[0]) == VOIDmode);
 
+  if (TARGET_PRFCHW && rw)
+    operands[2] = GEN_INT (3);
   /* Use 3dNOW prefetch in case we are asking for write prefetch not
      supported by SSE counterpart or the SSE prefetch is not available
      (K6 machines).  Otherwise use SSE prefetch as it allows specifying
      of locality.  */
-  if (TARGET_3DNOW && (!TARGET_PREFETCH_SSE || rw))
+  else if (TARGET_3DNOW && (!TARGET_PREFETCH_SSE || rw))
     operands[2] = GEN_INT (3);
   else
     operands[1] = const0_rtx;
@@ -17719,7 +17721,7 @@
   [(prefetch (match_operand:P 0 "address_operand" "p")
             (match_operand:SI 1 "const_int_operand" "n")
             (const_int 3))]
-  "TARGET_3DNOW"
+  "TARGET_3DNOW || TARGET_PRFCHW"
 {
   if (INTVAL (operands[1]) == 0)
     return "prefetch\t%a0";


Intrinsics for PREFETCHW

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